SG6846C Fairchild Semiconductor, SG6846C Datasheet - Page 3

• Manufacturer Part Number: SG6846C
• Description: The highly integrated PWM controller, SG6846C provides several features to enhance the performance of flyback converters
• Manufacturer: Fairchild Semiconductor

© 2007 Fairchild Semiconductor Corporation
SG6846C • Rev. 1.1.2
Marking Information
Pin Configuration
Pin Definitions
Pin #
1
2
3
4
5
6
7
8
SENSE
Name
GATE
GND
VDD
VIN
RT
FB
RI
Current Sense
Power Supply
Driver Output
Temperature
Line-voltage
Function
Reference
Feedback
Detection
Detection
Ground
Setting
Description
SG6846CFTP
Ground.
The signal from the external compensation circuit is fed into this pin. The
PWM duty cycle is determined in response to the signal from this pin and the
current-sense signal from pin 6.
Line-voltage detection, used for brownout protection with hysteresis. Constant
output power limit over universal AC input range is also achieved using this
pin. Add a low-pass filter to filter out line ripple on bulk capacitor.
A resistor from the RI pin to ground generates a reference current source that
determines the switching frequency. Increasing the resistance reduces the
switching frequency. Using a 26kΩ resistor results in a 65kHz switching
frequency.
For over-temperature protection, an external NTC thermistor is connected
from this pin to the GND pin. The impedance of the NTC decreases at high
temperatures. Once the voltage of the RT pin drops below a threshold, PWM
output is disabled.
Current sense. The sensed voltage is used for peak-current-mode control and
cycle-by-cycle current limiting. If the switching current is higher than OCP
threshold and lasts for 110ms, SG6846C turns off immediately. This two-level
OCP feature is especially suitable for SMPS with surge current output.
Power supply. If an open-circuit failure occurs in the feedback loop, the
internal protection circuit disables PWM output as long as V
threshold.
The totem-pole output driver for the power MOSFET. It is internally clamped
below 18V.
XXXXXXXXYWWV
GND
FB
VIN
RI
Figure 4. Pin Configuration
Figure 3. Top Mark
3
F: L
T: D = DIP, S = SOP
P :
XXXXXXXX: Wafer Lot
Y: Year; WW: Week
V: Assembly Location
Null = regular package
GATE
SENSE
VDD
RT
ROHS Compatible
Z = Lead Free +
= OCP Latch
DD
exceeds a
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