FAN6751MR Fairchild Semiconductor, FAN6751MR Datasheet - Page 10

• Manufacturer Part Number: FAN6751MR
• Description: The highly integrated FAN6751 series of PWM controllers provides several features to enhance the performance of flyback converters
• Manufacturer: Fairchild Semiconductor

© 2008 Fairchild Semiconductor Corporation
FAN6751MR • Rev. 1.0.0
Functional Description
Startup Current
For startup, the HV pin is connected to the line input
(1N4007 / 100KΩ recommended) or bulk capacitor
through a resistor, R
from pin HV is 2mA and charges the hold-up capacitor
through the diode and resistor. When the V
level reaches V
this moment, the V
FAN6751 to keep the V
the main transformer to provide the operating current.
Operating Current
Operating current is around 4mA. The low operating
current enables better efficiency and reduces the
requirement of V
Green-Mode Operation
The proprietary green-mode function provides off-time
modulation to reduce the switching frequency in the
light-load and no-load conditions. The on time is limited
for better abnormal or brownout protection. V
derived from the voltage feedback loop, is taken as the
reference. Once V
switching frequency is continuously decreased to the
minimum green-mode frequency of around 18KHz.
Current Sensing / PWM Current Limiting
Peak-current-mode control is utilized to regulate output
voltage and provide pulse-by-pulse current limiting. The
switch current is detected by a sense resistor into the
SENSE pin. The PWM duty cycle is determined by this
current sense signal and V
When the voltage on SENSE pin reaches around
V
immediately. V
voltage around 0.85V for output power limit.
Leading-Edge Blanking (LEB)
Each time the power MOSFET is switched on, a turn-on
spike occurs on the sense-resistor. To avoid premature
termination of the switching pulse, a leading-edge
blanking time is built in. During this blanking period, the
current-limit comparator is disabled and it cannot switch
off the gate driver.
Under-Voltage Lockout (UVLO)
The turn-on and turn-off thresholds are fixed internally
at 16.5V and 10.5V respectively. During startup, the
hold-up capacitor must be charged to 16.5V through the
startup resistor to enable the IC. The hold-up capacitor
continues to supply V
delivered from auxiliary winding of the main transformer.
V
This UVLO hysteresis window ensures that hold-up
capacitor is adequate to supply V
COMP
DD
must not drop below 10.5V during this process.
=(V
FB
–1.2)/4,
COMP
DD-ON
DD
FB
hold-up capacitance.
, the startup current switches off. At
is internally clamped to a variable
is lower than the threshold voltage,
a
HV
DD
DD
. Typical startup current drawn
DD
switch
capacitor only supplies the
before the auxiliary winding of
before the energy can be
FB
, the feedback voltage.
DD
cycle
during startup.
is
DD
FB
terminated
capacitor
, which is
10
Gate Output / Soft Driving
The BiCMOS output stage is a fast totem-pole gate
driver. Cross conduction has been avoided to minimize
heat dissipation, increase efficiency, and enhance
reliability. The output driver is clamped by an internal
18V Zener diode to protect power MOSFET transistors
against undesirable gate over voltage. A soft-driving
waveform is implemented to minimize EMI.
Soft-Start
For many applications, it is necessary to minimize the
inrush current at startup. The built-in 5ms soft-start
circuit significantly reduces the startup current spike
and output voltage overshoot.
Built-in Slope Compensation
The sensed voltage across the current-sense resistor is
used for peak-current-mode control and pulse-by-pulse
current limiting. Built-in slope compensation improves
stability
FAN6751 inserts a synchronized positive-going ramp at
every switching cycle.
Constant Output Power Limit
For constant output power limit over universal input-
voltage range, the peak-current threshold is adjusted by
the voltage of the VIN pin. Since the VIN pin is
connected to the rectified AC input line voltage through
the resistive divider, a higher line voltage generates a
higher V
the V
power at high-line input voltage equal to that at low-line
input. The value of R-C network should not be so large
it affects the power limit (shown as Figure 14). Usually,
R and C are less than 100Ω and 470pF, respectively.
IN
voltage increases, making the maximum output
IN
Figure 14. Current Sense R-C Filter
and
voltage. The threshold voltage decreases as
Blanking
prevents
SG5841
Circuit
Sense
Gate
sub-harmonic
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oscillation.