FAN302HL Fairchild Semiconductor, FAN302HL Datasheet - Page 13

• Manufacturer Part Number: FAN302HL
• Description: This highly integrated PWM controller, FAN302HL, provides several features to enhance the performance of general flyback converters
• Manufacturer: Fairchild Semiconductor

© 2010 Fairchild Semiconductor Corporation
FAN302HL • Rev. 1.0.1
V
V
output over-voltage conditions. Figure 34 shows the V
OVP protection method. When abnormal system
conditions occur that cause V
period of debounce time; PWM pulses are disabled and
FAN302HL enters Latch Mode until V
V
conditions are usually caused by open feedback loops
or abnormal behavior by the VS pin divider resistor.
S
S
DD-LH
Over-Voltage Protection (OVP)
over-voltage protection prevents damage due to
.
By that time, PWM pulses revive. V
Figure 33. Latch-Mode Operation
Figure 34. V
S
OVP Protection
S
to exceed 2.8V, after a
DD
drops to under
S
over-voltage
S
13
V
V
over-voltage conditions. When the V
26.5V due to abnormal conditions, PWM pulses are
disabled until the V
then starts again. Over-voltage conditions are usually
caused by open feedback loops.
Over-Temperature Protection (OTP)
The FAN302HL temperature-sensing circuit shuts down
PWM output if the junction temperature exceeds 140°C
(T
drops below the V
Leading-Edge Blanking (LEB)
Each time the power MOSFET is switched on, a turn-on
spike occurs at the sense resistor. To avoid premature
termination of the switching pulse, a 350ns leading-edge
blanking time is built in. Conventional RC filtering can
therefore be omitted. During this blanking period, the
current-limit comparator is disabled and it cannot switch
off the gate driver.
Under Voltage Lockout (UVLO)
The turn-on and turn-off thresholds are fixed internally at
16V and 5V, respectively. During startup, the hold-up
capacitor must be charged to 16V through the startup
resistor to enable the FAN302HL. The hold-up capacitor
continues to supply V
from the auxiliary winding of the main transformer. V
must not drop below 5V during this startup process. This
UVLO hysteresis window ensures that the hold-up
capacitor is adequate to supply V
Noise Immunity
Noise from the current sense or the control signal can
cause significant pulse-width jitter, particularly in
Continuous-Conduction
compensation helps alleviate these problems, further
precautions should still be taken. Good placement and
layout practices should be followed. Avoiding long PCB
traces and component leads, locating compensation
and filter components near the FAN302HL, and
increasing the power MOS gate resistance are advised.
DD
DD
OTP
Over-Voltage Clamping
over-voltage protection prevents damage due to
). The PWM pulses are disabled until V
DD-LH
DD
.
DD
voltage drops below the UVLO,
until power can be delivered
Mode.
DD
during startup.
DD
voltage exceeds
While
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DD
voltage
slope
DD