FDMF6820B Fairchild Semiconductor, FDMF6820B Datasheet - Page 16

• Manufacturer Part Number: FDMF6820B
• Manufacturer: Fairchild Semiconductor

© 2011 Fairchild Semiconductor Corporation
FDMF6820B • Rev. 1.0.2
PCB Layout Guidelines
Figure 31 and Figure 32 provide an example of a proper
layout for the FDMF6820B and critical components. All
of the high-current paths, such as VIN, VSWH, VOUT,
and GND copper, should be short and wide for low
inductance and resistance. This aids in achieving a
more stable and evenly distributed current flow, along
with enhanced heat radiation and system performance.
Recommendations for PCB Designers
1. Input ceramic bypass capacitors must be placed
2. The V
3. An output inductor should be located close to the
4. PowerTrench
5. VCIN, VDRV, and BOOT capacitors should be
6. Include a trace from the PHASE pin to the VSWH pin
7. The layout should include the option to insert a
addition to being the high-frequency current path
from the DrMOS package to the output inductor, it
serves as a heat sink for the low-side MOSFET in
the DrMOS package. The trace should be short and
wide enough to present a low-impedance path for
the high-frequency, high-current flow between the
DrMOS and inductor. The short and wide trace
minimizes electrical losses as well as the DrMOS
temperature rise. Note that the V
voltage and high-frequency switching node with high
noise potential. Care should be taken to minimize
coupling to adjacent traces. Since this copper trace
acts as a heat sink for the lower MOSFET, balance
using the largest area possible to improve DrMOS
cooling while maintaining acceptable noise emission.
FDMF6820B to minimize the power loss due to the
V
inductor dissipation does not heat the DrMOS.
stage and are effective at minimizing ringing due to
fast switching. In most cases, no VSWH snubber is
required. If a snubber is used, it should be placed
close to the VSWH and PGND pins. The selected
resistor and capacitor need to be the proper size for
power dissipation.
placed as close as possible to the VCIN-to-CGND,
VDRV-to-CGND, and BOOT-to-PHASE pin pairs to
ensure clean and stable power. Routing width and
length should be considered as well.
to improve noise margin. Keep this trace as short as
possible.
small-value series boot resistor between the boot
capacitor and BOOT pin. The boot-loop size,
including R
possible. The boot resistor may be required when
operating above 15V
the high-side MOSFET turn-on slew rate and V
overshoot. R
margin in synchronous buck designs that may have
close to the VIN and PGND pins. This helps reduce
the high-current power loop inductance and the input
current ripple induced by the power MOSFET
switching operation.
SWH
copper trace. Care should also be taken so the
SWH
BOOT
copper trace serves two purposes. In
®
BOOT
MOSFETs are used in the output
and C
can improve noise operating
IN
BOOT
and is effective at controlling
, should be as small as
SWH
node is a high-
SHW
16
8. The VIN and PGND pins handle large current
9. GND pad and PGND pins should be connected to
10. Ringing at the BOOT pin is most effectively
11. The SMOD# and DISB# pins have weak internal
12. Use multiple vias on the VIN and VOUT copper
noise issues due to ground bounce or high positive
and negative V
resistance lowers the DrMOS efficiency. Efficiency
versus noise trade-offs must be considered. R
values from 0.5Ω to 3.0Ω are typically effective in
reducing V
transients with frequency components greater than
100MHz. If possible, these pins should be connected
directly to the VIN and board GND planes. The use
of thermal relief traces in series with these pins is
discouraged since this adds inductance to the power
path. This added inductance in series with either the
VIN or PGND pin degrades system noise immunity
by increasing positive and negative V
the GND copper plane with multiple vias for stable
grounding. Poor grounding can create a noise
transient offset voltage level between CGND and
PGND. This could lead to faulty operation of the gate
driver and MOSFETs.
controlled by close placement of the boot capacitor.
Do not add an additional BOOT to the PGND
capacitor. This may lead to excess current flow
through the BOOT diode.
pull-up and pull-down current sources, respectively.
These pins should not have any noise filter
capacitors. Do not to float these pins unless
absolutely necessary.
areas to interconnect top, inner, and bottom layers
to distribute current flow and heat conduction. Do
not put many vias on the VSWH copper to avoid
extra parasitic inductance and noise on the
switching waveform. As long as efficiency and
thermal performance are acceptable, place only
one VSWH copper on the top layer and use no vias
on the VSWH copper to minimize switch node
parasitic noise. Vias should be relatively large and
of
frequency components, such as R
snubber, and bypass capacitors; should be located
as close to the respective DrMOS module pins as
possible on the top layer of the PCB. If this is not
feasible, they can be connected from the backside
through a network of low-inductance vias.
reasonably
SWH
overshoot.
SWH
low
ringing. Inserting a boot
inductance.
BOOT
SWH
Critical
, C
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ringing.
BOOT
high-
, RC
BOOT