FDMF6823A Fairchild Semiconductor, FDMF6823A Datasheet - Page 3

• Manufacturer Part Number: FDMF6823A
• Manufacturer: Fairchild Semiconductor

© 2011 Fairchild Semiconductor Corporation
FDMF6823A • Rev. 1.0.2
Pin Configuration
Pin Definitions
9 - 14, 42
5, 37, 41
15, 29 -
16 – 28
35, 43
Pin #
36
38
39
40
1
2
3
4
6
7
8
SMOD#
THWN#
PHASE Switch node pin for bootstrap capacitor routing. Electrically shorted to VSWH pin.
Name
VSWH
CGND IC ground. Ground return for driver IC.
PGND
DISB#
VDRV
BOOT
VCIN
PWM
VIN
GH
NC
GL
Figure 3.
When SMOD#=HIGH, the low-side driver is the inverse of the PWM input. When
SMOD#=LOW, the low-side driver is disabled. This pin has a 10µA internal pull-up current
source. Do not add a noise filter capacitor.
IC bias supply. Minimum 1µF ceramic capacitor is recommended from this pin to CGND.
Power for the gate driver. Minimum 1µF ceramic capacitor is recommended to be connected as
close as possible from this pin to CGND.
Bootstrap supply input. Provides voltage supply to the high-side MOSFET driver. Connect a
bootstrap capacitor from this pin to PHASE.
For manufacturing test only. This pin must float; it must not be connected to any pin.
No connect. The pin is not electrically connected internally, but can be connected to VIN for
convenience.
Power input. Output stage supply voltage.
Switch node input. Provides return for high-side bootstrapped driver and acts as a sense point
for the adaptive shoot-through protection.
Power ground. Output stage ground. Source pin of the low-side MOSFET.
For manufacturing test only. This pin must float; it must not be connected to any pin.
Thermal warning flag, open collector output. When temperature exceeds the trip limit, the
output is pulled LOW. THWN# does not disable the module.
Output disable. When LOW, this pin disables the power MOSFET switching (GH and GL are
held LOW). This pin has a 10µA internal pull-down current source. Do not add a noise filter
capacitor.
PWM signal input. This pin accepts a three-state 5V PWM signal from the controller.
Bottom View
3
Description
Figure 4.
Top View
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