FAN3121T Fairchild Semiconductor, FAN3121T Datasheet - Page 15
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FAN3121T
Manufacturer Part Number
FAN3121T
Description
The FAN3121 and FAN3122 MOSFET drivers are designed to drive N-channel enhancement MOSFETs in low-side switching applications by providing high peak current pulses
Manufacturer
Fairchild Semiconductor
Datasheet
1.FAN3122T.pdf
(21 pages)
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
FAN3121TMX
Manufacturer:
FAIRCHILD/仙童
Quantity:
20 000
© 2008 Fairchild Semiconductor Corporation
FAN3121 / FAN3122 • Rev. 1.0.0
Figure 47 shows the pulsed gate drive current path
when the gate driver is supplying gate charge to turn
the MOSFET on. The current is supplied from the local
bypass capacitor C
the MOSFET gate and to ground. To reach the high
peak currents possible with the FAN312x family, the
resistance and inductance in the path should be
minimized. The localized C
peak current pulses within this driver-MOSFET circuit,
preventing them from disturbing the sensitive analog
circuitry in the PWM controller.
Figure 48 shows the path the current takes when the gate
driver turns the MOSFET off. Ideally, the driver shunts the
current directly to the source of the MOSFET in a small
circuit loop. For fast turn-off times, the resistance and
inductance in this path should be minimized.
Operational Waveforms
At power up, the FAN3121 inverting driver shown in
Figure 49 holds the output LOW until the V
reaches the UVLO turn-on threshold, as indicated in
Figure 50. This facilitates proper startup control of low-
side N-channel MOSFETs.
The OUT pulses’ magnitude follows V
the output polarity inverted from the input until steady-
state V
Figure 48. Current Path for MOSFET Turn-Off
Figure 47. Current Path for MOSFET Turn-On
DD
Figure 49. Inverting Configuration
is reached.
PWM
PWM
C
C
BYP
BYP
IN
BYP
and flows through the driver to
V
V
V
DD
DD
BYP
DD
FAN3121/2
FAN3121/2
acts to contain the high
OUT
DD
magnitude with
V
V
DS
DS
DD
voltage
At power up, the FAN3122 non-inverting driver, shown
in Figure 51, holds the output LOW until the V
reaches the UVLO turn-on threshold, as indicated in
Figure 52. The OUT pulses magnitude follow V
magnitude until steady-state V
(V
IN+
V
OUT
IN-
15
IN+
DD
V
DD
IN-
OUT
DD
Figure 52. Non-Inverting Startup Waveforms
)
Figure 50. Inverting Startup Waveforms
Figure 51. Non-Inverting Driver
IN
V
DD
DD
is reached.
OUT
Turn-on threshold
Turn-on threshold
www.fairchildsemi.com
DD
voltage
DD