FSB50450TB Fairchild Semiconductor, FSB50450TB Datasheet - Page 12

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FSB50450TB

Manufacturer Part Number
FSB50450TB
Description
Manufacturer
Fairchild Semiconductor
Datasheet

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FSBB15CH60BT Rev. C
Note:
1) RC coupling at each input might change depending on the PWM control scheme used in the application and the wiring impedance of the application’s printed circuit board. The
2) The logic input is compatible with standard CMOS or LSTTL outputs.
Note:
1) The ceramic capacitor placed between V
SPM input signal section integrates 5k Ω ( typ.) pull-down resistor. Therefore, when using an external filtering resistor, please pay attention to the signal voltage drop at input ter-
minal.
CPU
15V-Line
Figure 12. Recommended Bootstrap Operation Circuit and Parameters
These Values depend on PWM Control Algorithm
1000uF
Figure 11. Recommended CPU I/O Interface Circuit
CC
22uF
-COM should be over 1uF and mounted as close to the pins of the SPM as possible.
1nF
100Ω
100Ω
100Ω
R
C
0.1uF
PF
PF
=4.7㏀
= 1nF
1uF
5V-Line
12
One-Leg Diagram of SPM
1nF
IN
COM
IN
Vcc
Vcc
COM
OUT
HO
VS
VB
V
SL
1nF
COM
IN
IN
V
P
N
FO
(UH)
(UL)
Inverter
Output
,
,
IN
IN
(VH)
(VL)
SPM
,
,
IN
IN
(WH)
(WL)
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