FPF1320 Fairchild Semiconductor, FPF1320 Datasheet - Page 13

• Manufacturer Part Number: FPF1320
• Description: The FPF1320/21 is a Dual-Input Single-Output (DISO) load switch consisting of two sets of slew-rate controlled, low on-resistance, P-channel MOSFET switches and integrated analog features
• Manufacturer: Fairchild Semiconductor

© 2011 Fairchild Semiconductor Corporation
FPF1320 / FPF1321 • Rev. 1.0.0
Operation and Application Description
The FPF1320 and FPF1321 are dual-input single-output
power multiplexer switches with controlled turn-on and
seamless power source transition. The core is a 50mΩ
P-channel
functioning over a wide input operating range of 1.5V to
5.5V per channel. The EN and SEL pins are active-
HIGH, GPIO/CMOS-compatible input. They control the
state of the switch and input power source selection,
respectively.
reverse current during both ON and OFF states when
higher V
65Ω output discharge path during off.
Input Capacitor
To limit the voltage drop on the input supply caused by
transient inrush current when the switch turns on into a
discharged load capacitor; a capacitor must be placed
between the V
1µF ceramic capacitor, C
usually sufficient. Higher-value C
reduce more the voltage drop.
Inrush Current
Inrush current occurs when the device is turned on.
Inrush current is dependent on output capacitance and
slew rate control capability, as expressed by:
Higher inrush current causes higher input voltage drop,
depending on the distributed input resistance and input
capacitance. High inrush current can cause problems.
FPF1320/1 has a 130µs of slew rate capability under
3.3V
and input voltage drop can be minimized.
where:
C
t
V
V
I
R
LOAD
I
IN
INITIAL
OUT
:
INRUSH
IN
:
at 1µF of C
:
:
OUT
: Initial voltage at C
Output capacitance;
Slew rate or rise time at V
Input voltage, V
Load current.

than V
MOSFET
C
IN
TRCB
OUT
A or V
IN
OUT
A or V

V
and 150Ω of R
IN
functionality
IN
B pins to the GND pin. At least
and
IN
IN
IN

, placed close to the pins, is
A or V
B is applied. FPF1321 has a
OUT
t
V
R
INITIAL
, usually GND; and
controller
IN
B;
IN
OUT

L
blocks
can be used to
;
so inrush current
I
LOAD
capable
unwanted
(1)
of
13
Power Source Selection
Input power source selection can be controlled by the
SEL pin. When SEL is LOW, output is powered from
V
SEL signal is ignored during device OFF.
Output Voltage Drop during Transition
Output voltage drop usually occurs during input power
source transition period from low voltage to high
voltage. The drop is highly dependent on output
capacitance and load current.
FPF1320/1 adopts an advanced break-before-make
control, which can result in minimized output voltage
drop during the transition time.
Output Capacitor
Capacitor C
between the V
output voltage drop during input power source transition.
This capacitor also prevents parasitic board inductance.
True Reverse-Current Blocking
The true reverse-current blocking feature protects the
input source against current flow from output to input
regardless of whether the load switch is on or off.
Board Layout
For best performance, all traces should be as short as
possible. To be most effective, the input and output
capacitors should be placed close to the device to
minimize the effect that parasitic trace inductance on
normal and short-circuit operation. Wide traces or large
copper planes for power pins (V
GND) minimize the parasitic electrical effects and the
thermal impedance.
IN
A while SEL is HIGH, V
OUT
OUT
of at least 1µF is highly recommended
and GND pins to achieve minimized
IN
B is powering output. The
IN
A, V
IN
B, V
www.fairchildsemi.com
OUT
and