FAN5400 Fairchild Semiconductor, FAN5400 Datasheet - Page 25
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FAN5400
Manufacturer Part Number
FAN5400
Description
The FAN5400 combines a highly integrated switched-mode charger, to minimize single-cell Lithium-ion (Li-ion) charging time from a USB power source, and a boost regulator to power a USB peripheral from the battery
Manufacturer
Fairchild Semiconductor
Datasheet
1.FAN5400.pdf
(37 pages)
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Additional
evaluation board, are given in Table 11 (measured with
T
effective
the die temperature and its ambient.
Table 11. FAN5400 Evaluation Board Measured
Charge Mode Input Supply Protection
Sleep Mode
When V
V
draining into VBUS. During Sleep Mode, reverse current is
disabled by body switching Q1.
Input Supply Low-Voltage Detection
The IC continuously monitors VBUS during charging. If V
falls below V
If V
t
This function prevents the USB power bus from collapsing or
oscillating when the IC is connected to a suspended USB
port or a low-current-capable OTG device.
Input Over-Voltage Detection
When the V
When V
cleared and charging resumes after V
VBUS POR / Non-Compliant Charger Rejection).
VBUS Short While Charging
If VBUS is shorted with a very low impedance while the IC is
charging with I
specifications until power is removed. To trigger this
condition, V
slew rate. Achieving this slew rate requires a 0 short to the
USB cable less than 10cm from the connector.
Charge Mode Battery Detection & Protection
VBAT Over-Voltage Protection
The OREG voltage regulation loop prevents V
overshooting the OREG voltage by more than 50mV when
the battery is removed. When the PWM charger runs with no
battery, the TE bit is not set and a battery is inserted that is
charged to a voltage higher than V
no further pulses occur for 30ms, the IC sets the FAULT bits
to 100, sets the STAT bits to 11, and pulses the STAT pin.
© 2009 Fairchild Semiconductor Corporation
FAN5400 Family • Rev. 1.0.7
2.
INT
3.
1.
1.
2.
A
IN(MIN),
=25°C). Note that as power dissipation increases, the
BUS
(about two seconds), the charging process is repeated.
Terminates charging
Pulses the STAT pin, sets the STAT bits to 11, and sets
the FAULT bits to 011.
Turns off Q3
Suspends charging
Sets the FAULT bits to 001, sets the STAT bits to 11,
and pulses the STAT pin.
recovers above the V
the IC enters Sleep Mode to prevent the battery from
BUS
BUS
Power (W)
JA
0.504
0.844
1.506
BUS
BUS
JA
falls about 150mV below VBUS
decreases due to the larger difference between
IN(MIN)
falls below V
INLIMIT
data points, measured using the FAN540X
exceeds VBUS
must be driven from 5V to GND with a high
, the IC:
=100mA, the IC may not meet datasheet
BAT
IN(MIN)
OVP
+ V
, the IC:
OREG
rising threshold after time
SLP
BUS
, and V
; PWM pulses stop. If
54°C/W
50°C/W
46°C/W
is revalidated (see
OVP
JA
BUS
, the fault is
is above
BAT
from
BUS
JA
25
Battery Detection During Charging
The IC can detect the presence, absence, or removal of a
battery if the termination bit (TE) is set. During normal
charging, once V
charge current is detected, the IC terminates charging and
sets the STAT bits to 10. It then turns on a discharge current,
I
battery is present and the IC sets the FAULT bits to 000. If
V
Battery Short-Circuit Protection
If the battery voltage is below the short-circuit threshold
(V
V
Battery Detection During Power-up
For FAN5400 and FAN5403
At VBUS POR, a 5K load is applied to VBAT for 500ms to
discharge any residual system capacitance in case the
battery is absent. If V
commences. When V
proceeds with the float voltage (OREG) temporarily set to
4V. If the battery voltage exceeds 3.7V within 32ms of the
beginning of PWM charging, the battery is absent. If battery
absent is detected:
If V
float voltage returns to the OREG register setting and PWM
charging continues.
System Operation with No Battery
The FAN5402 and FAN5405 continue charging after VBUS
POR with the default parameters, regulating the V
3.54V until the host processor issues commands or the 15-
minute timer expires. In this way, the FAN5402 and
FAN5405 can start the system without a battery.
The FAN540X soft-start function can interfere with the
system supply with battery absent. The soft-start activates
whenever V
higher value. During soft-start, the I
for about 1ms unless I
cause the system processor to fail to start. To avoid this
behavior, use the following sequence.
1.
2.
3.
4.
5.
6.
DETECT
1.
2.
3.
1.
2.
3.
BAT
BAT
SHORT
BAT
Set the OTG pin HIGH. When VBUS is plugged in, I
is set to 500mA until the system processor powers up
and can set parameters through I
Program the Safety Register.
Set I
Set OREG to the desired value (typically 4.18).
Reset the IOLEVEL bit, then set IOCHARGE.
Set I
is below V
Sets the registers to their default values.
Sets the FAULT bits to 111.
Resumes charging with default values after t
> V
High-Impedance Mode is entered.
FAULT bits are set to 111.
The t
, for t
remains below 3.7V during the initial 32ms period, the
); a linear current source, I
SHORT
INLIM
INLIM
15MIN
OREG
DETECT
to 11 (no limit).
.
to 500mA if a USB source is connected.
OREG
timer is disabled until VBUS is removed.
, I
BAT
. If V
INLIM
– V
BAT
is close to V
, or I
INLIM
RCH
BAT
rises above V
BAT
, the battery is absent and the IC:
is set to 11 (no limit). This could
is still above V
OCHARGE
< V
OREG
SHORT
SHORT
are set from a lower to
IN
2
C.
SHORT
limit drops to 100mA
and the termination
, supplies V
, linear charging
www.fairchildsemi.com
OREG
, PWM charging
– V
INT
BAT
.
RCH
BAT
line to
, the
INLIM
until