STG3000X-RIVA128 STMicroelectronics, STG3000X-RIVA128 Datasheet - Page 16

• Manufacturer Part Number: STG3000X-RIVA128
• Description: 128-BIT 3D MULTIMEDIA ACCELERATOR
• Manufacturer: STMicroelectronics

RIVA 128
the AGP bridge chip and RIVA 128 are the only
devices on the AGP bus - all other I/O devices re-
main on the PCI bus.
The add-in slot defined for AGP uses a new con-
nector body (for electrical signaling reasons)
which is not compatible with the PCI connector;
PCI and AGP boards are not mechanically inter-
changeable.
AGP accesses differ from PCI in that they are
pipelined. This compares with serialized PCI
4.1
The RIVA 128 glueless interface to AGP 1.0 is shown in Figure 2.
Figure 2. AGP interface pin connections
4.2
AGP bus commands supported
The following AGP bus commands are supported
by the RIVA 128:
16/77
- Read
- Read (hi-priority)
RIVA 128 AGP INTERFACE
AGP BUS TRANSACTIONS
PCICBE[3:0]#
PCIDEVSEL#
AGPST[2:0]#
PCIAD[31:0]
AGPPIPE#
PCITRDY#
PCISTOP#
AGPRBF#
PCIIRDY#
PCIIDSEL
PCIINTA#
PCIREQ#
PCIGNT#
PCIRST#
PCIPAR
PCICLK
32
4
3
128-BIT 3D MULTIMEDIA ACCELERATOR
transactions, where the address, wait and data
phases need to complete before the next transac-
tion starts. AGP transactions can only access sys-
tem memory - not other PCI devices or CPU. Bus
mastering accesses can be either PCI or AGP-
style.
Full details of AGP are given in the Accelerated
Graphics Port Interface Specification [3] published
by Intel Corporation.
PCI transactions on the AGP bus
PCI transactions can be interleaved with AGP
transactions including between pipelined AGP
data transfers. A basic PCI transaction on the AGP
interface is shown in Figure 3. If the PCI target is
a non AGP compliant master, it will not see
AGPST[2:0] and the transaction appears to be on
a PCI bus. For AGP aware bus masters,
AGPST[2:0] indicate that permission to use the in-
terface has been granted to initiate a request and
not to move AGP data.
RIVA 128