STG3000X-RIVA128 STMicroelectronics, STG3000X-RIVA128 Datasheet - Page 33

• Manufacturer Part Number: STG3000X-RIVA128
• Description: 128-BIT 3D MULTIMEDIA ACCELERATOR
• Manufacturer: STMicroelectronics

128-BIT 3D MULTIMEDIA ACCELERATOR
Figure 28. SGRAM read to write, read latency of three
Table 7. SGRAM I/O timing parameters
Figure 29. SGRAM random write cycles within a page
NOTE
Figure 30. SGRAM write to read cycle
NOTE
Symbol
t
t
HZ
DS
1
1
Covers either successive writes to the active row in a given bank or to the active row s in different banks. F BDQ M is active
(low).
A read latency of 2 is shown for illustration
Command
Command
FBD[63:0]
Command
FBD[63:0]
FBD[63:0]
FBA[9:0]
FBA[9:0]
FBCLKx
FBA[9:0]
FBCLKx
Data out high impedance time
Write data setup time
FBCLKx
TDDQM
write
data n
bank,
col n
write
bank, col n
bank, col n
Parameter
data n
write
read
write
data n
nop
bank, col a
nop
data a
write
bank,
col b
read
Min.
nop
4
4
bank, col x
nop
data x
write
read
data b
Max.
nop
10
nop
read data n
t
bank, col m
HZ
data m
write
nop
Unit
bank, col b
ns
ns
write
write data b
t
DS
RIVA 128
Notes
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