STG3000X-RIVA128 STMicroelectronics, STG3000X-RIVA128 Datasheet - Page 65

• Manufacturer Part Number: STG3000X-RIVA128
• Description: 128-BIT 3D MULTIMEDIA ACCELERATOR
• Manufacturer: STMicroelectronics

128-BIT 3D MULTIMEDIA ACCELERATOR
Bits
7:6
8
5
4
3
2
1
0
Function
SERR_ENABLE is an enable bit for the SERR# driver.
0=Disables the SERR# driver
1=Enables the SERR# driver
Reserved
PALETTE_SNOOP indicates that VGA compatible devices should snoop their
palette registers.
0=Palette accesses treated like all other accesses
1=Enables special palette snooping behavior
WRITE_AND_INVAL is an enable bit for using the Memory Write and Invali-
date command.
1=The RIVA 128 as bus master may generate the command
0=The Memory Write command must be used instead of Memory Write and
Invalidate
Reserved
BUS_MASTER indicates that the device can act as a master on the PCI bus.
0=Disables the RIVA 128 from generating PCI accesses
1=Allows the RIVA 128 to behave as a bus master
MEMORY_SPACE indicates that the RIVA 128 will respond to memory space
accesses .
0=Device response disabled
1=Enables response to Memory space accesses. The device will decode and
respond to the 16MByte ranges as well as the default VGA memory range
when it is enabled. The VGA decode range may change based upon the
value in the VGA graphics Miscellaneous Register GR06, bits[3:2] and other
enable bits, see RIVA 128 Programming Reference Manual [2].
IO_SPACE indicates that the device will respond to I/O space accesses . This
bit enables I/O space accesses for the VGA function as defined in the PCI
specific ation. These include 0x3B0 - 0x3BB, 0x3C0 - 0x3DF and their aliases.
RIVA 128
R W 0
R W 0
R W 0
R W 0
R W 0
R W 0
R W I
R - 0
R - 0
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