STG3000X-RIVA128 STMicroelectronics, STG3000X-RIVA128 Datasheet - Page 69

• Manufacturer Part Number: STG3000X-RIVA128
• Description: 128-BIT 3D MULTIMEDIA ACCELERATOR
• Manufacturer: STMicroelectronics

128-BIT 3D MULTIMEDIA ACCELERATOR
Byte offsets 0x17 - 0x14
Base Memory Address Register (0x17 - 0x14)
Byte offsets 0x2B - 0x18
Base Address Registers (0x2B - 0x18)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
31:24
Bits
23:4
Bits
31:0
2:1
3
0
0x17
Function
The BASE_ADDRESS bits contain the most significant bits of the base
address of the device. This indicates that the RIVA 128 requires a 16MByte
block of contiguous memory beginning on a 16MByte boundary. This memory
range contains linear frame buffer access and may be set as part of a Pen-
tiumPro ’s write combining (wc) range.
The BASE_RESERVED bits form the least significant bits of the base address
and are hardwired to 0.
The PREFETCHABLE bit indicates that there are no side effects on reads,
that the device returns all bytes on reads regardless of the byte enables, and
that host bridges can merge processor writes into this range without causing
errors.
The ADDRESS_TYPE bits contain the type (width) of the Base Address.
0=32-bit
The SPACE_TYPE bit indicates whether the register maps into Memory or I/O
space.
0=Memory space
Function
These bits are hardwired (read-only) to 0.
0x16
0x00000000
0x15
9
9
8
8
7
7
6
6
5
5
0x14
4
4
RIVA 128
3
3
R W 0
R W I
R W I
R - 0
R - 1
R - 0
R - 0
R - 0
2
2
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1
1
0
0