STG3000X-RIVA128 STMicroelectronics, STG3000X-RIVA128 Datasheet - Page 30

• Manufacturer Part Number: STG3000X-RIVA128
• Description: 128-BIT 3D MULTIMEDIA ACCELERATOR
• Manufacturer: STMicroelectronics

RIVA 128
Table 5. Truth table of supported SGRAM commands
NOTES
6.1
SGRAMs must be powered-up and initialized in a predefined manner. The first SGRAM command is reg-
istered on the first clock edge following PCIRST# inactive.
All internal SGRAM banks are precharged to bring the device(s) into the “all bank idle” state. The SGRAM
mode registers are then programmed and loaded to bring them into a defined state before performing any
operational command.
6.2
The Mode register defines the mode of operation of the SGRAM. This includes burst length, burst type,
read latency and SGRAM operating mode. The Mode register is programmed via the Load Mode register
and retains its state until reprogrammed or power-down.
Mode register bits M[2:0] specify the burst length; for the RIVA 128 SGRAM interface these bits are set to
zero, selecting a burst length of one. In this case FBA[7:0] select the unique column to be accessed and
Mode register bit M[3] is ignored. Mode register bits M[6:4] specify the read latency; for the RIVA 128
SGRAM interface these bits are set to either 2 or 3, selecting a burst length of 2 or 3 respectively.
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Command
Command inhibit (NOP)
No operation (NOP)
Active (select bank and
activate row)
Read (select bank and
column and start read
burst)
Write (select bank and
column and start write
burst)
Precharge (deactivate
row in both banks)
Load mode register
Write enable/output
enable
Write inhibit/output
High-Z
SGRAM INITIALIZATION
SGRAM MODE REGISTER
1
2
FBCK E is high and DSF is low for all supported commands.
Activates or deactivates FBD[12 7:0] during writes (zero clock delay) and read s (two-clock delay).
1
FBCSx
H
L
L
L
L
L
L
-
-
FBRAS# FBCAS# FBWE#
H
H
H
L
L
L
x
-
-
H
H
H
x
L
L
L
-
-
128-BIT 3D MULTIMEDIA ACCELERATOR
H
H
H
x
L
L
L
-
-
FBDQM
H
L
x
x
x
x
x
x
x
FBA[9:0]
FBA[8:0] =row
FBA[7:0] =row
FBA[7:0]=row
FBA[9] =bank
FBA[9] =bank
FBA[9] =bank
FBA[8:0] =
FBA[8]=0
FBA[8] =0
FBA[8]=1
opcode
x
x
-
-
FBD[63:0] Notes
valid data
high-Z
active
x
x
x
x
x
2
2