ATA6613 ATMEL Corporation, ATA6613 Datasheet
ATA6613
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ATA6613 Summary of contents
Page 1
... AVR 8-bit microcontroller with advanced RISC architecture. The ATA6612 consists of the LIN-SBC ATA6624 and the ATmega88 with 8 Kbytes flash. The ATA6613 consists of the LIN-SBC ATA6624 and the ATmega168 with 16 Kbytes flash. All pins of the LIN System Basis Chip as well as all pins of the AVR microcontroller are bonded out to provide customers the same flexibility for their appli- cations as they have when using discrete parts ...
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... INH High side switch output for controlling an external voltage regulator (1) 19 TXD Transmit data input / active low output after a local wake up request Note: 1. This identifies the pins of the LIN SBC ATA6624 ATA6612/ATA6613 PB5 1 MCUAVDD 2 ...
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... Port B 0 I/O line (ICP1/CLKO/PCINT0) 45 PB1 Port B 1 I/O line (OC1A/PCINT1) 46 PB2 Port B 2 I/O line (OC1B/SS/PCINT2) 47 PB3 Port B 3 I/O line (MOSI/OC2A/PCINT3) 48 PB4 Port B 4 I/O line (MISO/PCINT4) Backside Heat slug is connected to GND Note: 1. This identifies the pins of the LIN SBC ATA6624 9111C–AUTO–02/08 ATA6612/ATA6613 3 ...
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... Thermal resistance junctiion to ambient, according to JEDEC Thermal shutdown of VCC regulator Thermal shutdown of LIN output Thermal shutdown hysteresis Note means the temperature of the heat slug (backside mandatory that this backside temperature is 125°C in the case application. ATA6612/ATA6613 4 Symbol Min. Typ. ±2 ±750 T – – ...
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... The LIN-SBC are designed to handle the low-speed data communication in vehicles, e.g., in convenience electronics. Improved slope control at the LIN-driver ensures secure data commu- nication kBaud. Sleep Mode and Silent Mode guarantee very low current consumption. 9111C–AUTO–02/ 27V S is Switched Off CC ATA6612/ATA6613 5 ...
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... INH PVCC 17 RXD 30 WAKE 24 Edge KL_15 Detection PVCC TXD 19 Time-out TXD Timer 28 Debounce EN Time 31 GND ATA6612/ATA6613 6 Receiver Wake-up Bus Timer Slew Rate Control Control Unit Mode Select Internal Testing Watchdog Unit PVCC MODE TM NTRIG Normal and Fail-safe Mode RF Filter Short Circuit and ...
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... LIN protocol specification. The fall time from recessive to dominant bus state and the rise time from dominant to recessive bus state are slope controlled. 9111C–AUTO–02/ 27V. An undervoltage detection is implemented to dis- S falls below boost up the maximum load current, an external NPN transistor may be used, with ATA6612/ATA6613 < order to avoid false bus messages. After th 7 ...
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... To debug the software of the connected microcontroller, connect MODE pin to 3.3V/5V and the watchdog is switched off. 3.3.13 TM Input Pin The TM pin is used for final production measurements at Atmel. In normal application, it has to be always connected to GND. ATA6612/ATA6613 8 > 6 ms, the DOM = 0V). S typ. 57 µA. The VCC VS 9111C– ...
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... IC into Sleep or Silent Mode. Connect the KL_15 pin Batt . To protect this pin against voltage transients, a serial resistor and a ceramic and, therefore, the sensitivity against transients on the ignition Kl.30. KL_15 to generate a watchdog trigger. trigmin ATA6612/ATA6613 of 160 µs is Kl_15 undervoltage ...
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... NRES is switched to low, and the IC changes its state to Fail-safe Mode. With EN high, you can switch directly from Silent mode to Normal mode. A voltage less than the LIN Pre_Wake detection VLINL at the LIN pin activates the internal LIN receiver. ATA6612/ATA6613 10 Unpowered Mode V ...
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... Mode select window TXD t = 3.2 µs d NRES VCC Delay time silent mode t _sleep = maximum 20 µs d LIN LIN switches directly to recessive mode ) and the following rising edge at the LIN pin (see bus ATA6612/ATA6613 Silent Mode Figure 3-4 on page 12) result in a Figure 3-4 on page 12). EN high can be 11 ...
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... A voltage less than the LIN Pre_Wake detection VLINL at the LIN pin activates the internal LIN receiver. A falling edge at the LIN pin followed by a dominant bus level maintained for a certain time period (t device switches from Sleep Mode to Fail-safe Mode. ATA6612/ATA6613 12 LIN Wake-up from Silent Mode Bus wake-up filtering time t ...
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... LIN communication is res (V < 4V) during Silent or Sleep Mode switches the IC into Batt S Figure 3-7 on page , the IC mode changes from Unpowered Mode to Fail-safe Mode. th ATA6612/ATA6613 Sleep Mode Figure 3-7 on page 17). The NRES output 17). After VS is higher than the VS . This time depends on the VCC VCC ...
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... Figure 3-6. Table 3-1. Mode of Operation Fail-safe Normal Silent Sleep ATA6612/ATA6613 14 LIN Wake-up from Sleep Mode Normal Mode EN Mode select window TXD t = 3.2 µs d NRES VCC Delay time sleep mode t = maximum 20 µs d_sleep LIN LIN switches directly to recessive mode Table of Modes Transceiver VCC Watchdog Off 3 ...
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... LIN result in a remote wake-up request. The device BUS and Figure 3-4 on page 12) and the Normal Mode. The last wake-up ATA6612/ATA6613 at the LIN pin activates the internal LIN LINL maintained for a certain BUSdom ) KL_15 ...
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... C > 10 µF and a ceramic capacitor with C = 100 nF. The values of these capacitors can be var- ied by the customer, depending on the application. The main power dissipation of the IC is created from the VCC output current I needed for the application. ATA6612/ATA6613 16 , the output limits the output current to I Battery ...
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... T T VCC Reset NRES 5V/3.3V . The trigger signal must exceed a minimum time 120 After wake up from Sleep or Silent Mode, the lead time d ATA6612/ATA6613 T res_f Pin of the system basis chip is disconnected adjustable via the external resistor osc ...
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... If the triggering signal fails in this open window t output will be drawn to ground. A triggering signal during the closed window t switches NRES to low. Figure 3-8. VCC 3.3V 5V NRES NTRIG ATA6612/ATA6613 WD_OSC is adjustable between 20 ms and 64 ms using the external resistor – 0.0004 ...
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... Typical Watchdog Timings Oscillator Lead Closed Period Time Window t /µs t /ms t /ms osc d 1 13.3 105 14.0 19.61 154.8 20.64 33.54 264.80 35.32 42.84 338.22 45.11 ATA6612/ATA6613 and t can also vary by 20 calculated as follows. wd and the minimum 24 Trigger Period from Open Window Microcontroller t / 14.7 19.9 21.67 29.32 37.06 50.14 47.34 64.05 ...
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... Test Spec. 1.0 following IEC 61000-4-2 - Pin VS, LIN to GND - Pin WAKE (33 k serial resistor) to GND ESD HBM following STM5.1 with 1.5 k 150 pF - Pin VS, LIN, WAKE to GND Junction temperature Storage temperature Thermal shutdown of VCC regulator Thermal shutdown of LIN output Thermal shutdown hysteresis ATA6612/ATA6613 20 Symbol Min. V –0 – ...
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... RXD LIN = 0.4V RXD = 1 mA RXD RXD TXD TXD = 0V TXD TXD = VCC TXD TXD = V LIN S TXD = 0V WAKE = 0.4V TXD ATA6612/ATA6613 Symbol Min. Typ. Max VSsleep VSsleep VSsi VSsi I 0 ...
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... The serial diode is 8.6 Pull-up resistor mandatory LIN current limitation 8 BUS Batt_max *) Type means 100% tested 100% correlation tested Characterized on samples Design parameter ATA6612/ATA6613 22 < 150°C, unless otherwise specified. All values refer to GND pins j Pin ...
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... BUS = BUS_CNT LIN + V _ )/2 th_dom th rec = 5V LIN LIN – V LIN hys th_rec th_dom LIN LIN = 0V LIN = TXD ATA6612/ATA6613 Symbol Min. Typ. Max. –1 –0. BUS_PAS_rec –10 +0.5 +10 BUS_NO_gnd BUS 0.475 0.5 0.525 V BUS_CNT 0.4 BUSdom V ...
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... Low-level output low V V 12.3 Undervoltage reset time C Reset debounce time for V 12.4 falling edge C *) Type means 100% tested 100% correlation tested Characterized on samples Design parameter ATA6612/ATA6613 24 < 150°C, unless otherwise specified. All values refer to GND pins j Pin = 0.744 V Rec(max 0.581 ...
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... All values refer to GND pins j Pin = –200 µ OSC = 51 k OSC = 91 k OSC = 120 k OSC OSC < 27V S = 27V KL_15 = 100 nF V < 27V WAKE = 27V S = 27V WAKE = 0V WAKE ATA6612/ATA6613 Symbol Min. Typ. Max. V 1.13 1.23 1.33 WD_OSC R 34 120 OSC t 10.65 13.3 15.97 OSC t 15.68 19.6 23.52 OSC t 26.83 33.5 40.24 OSC t 34.2 42 ...
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... V Ramp-up time V > 5. 18. load *) Type means 100% tested 100% correlation tested Characterized on samples Design parameter ATA6612/ATA6613 26 < 150°C, unless otherwise specified. All values refer to GND pins j Pin < 18V S < 5.5V S > –20 mA > –50 mA > ...
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... VS TH Dom(max) (Transceiver supply of transmitting node) TH Rec(min) TH Dom(min) RXD (Output of receiving node1) t rx_pdf(1) RXD (Output of receiving node2) 9111C–AUTO–02/ Bit Bit t Bus_dom(max) LIN Bus Signal t Bus_dom(min) t rx_pdr(2) ATA6612/ATA6613 t Bit t Bus_rec(min) Thresholds of receiving node1 Thresholds of receiving node2 t Bus_rec(max) t rx_pdr(1) t rx_pdf(2) 27 ...
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... MIPS Throughput at 16 MHz – On-chip 2-cycle Multiplier • Non-volatile Program and Data Memories – 8/16 Kbytes of In-System Self-programmable Flash (ATA6612/ATA6613) Endurance: 75,000 Write/Erase Cycles – Optional Boot Code Section with Independent Lock Bits In-System Programming by On-chip Boot Program True Read-While-Write Operation – ...
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... Overview The ATA6612/ATA6613 uses a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATA6612/ATA6613 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. 6.2.1 Block Diagram Figure 6-1 ...
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... ISO-TS-16949 grade 1. This data sheet con- tains limit values extracted from the results of extensive characterization (Temperature and Voltage). The quality and reliability of the ATA6612 and ATA6613 have been verified during reg- ular product qualification as per AEC-Q100. ...
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... Comparison Between ATA6612/ATA6613 The ATA6612 and ATA6613 differ only in memory sizes, boot loader support, and interrupt vec- tor sizes. devices. Table 6-1. Device ATA6612 ATA6613 ATA6612 and ATA6613 support a real Read-While-Write Self-Programming mechanism. There is a separate Boot Loader Section, and the SPM instruction can only execute from there. ...
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... ADC7:6 (TQFP and QFN Package Only) In the TQFP and QFN package, ADC7:6 serve as analog inputs to the A/D converter. These pins are powered from the analog supply and serve as 10-bit ADC channels. ATA6612/ATA6613 32 Table 6-3 on page , even if the ADC is not used. If the ADC is used, it should be connected ...
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... Instruction register Instruction decoder Control lines 9111C–AUTO–02/08 Data Bus 8-bit Program Status counter and control 32 8 general purpose registers ALU DATA SRAM EEPROM I/O lines ATA6612/ATA6613 Interrupt unit SPI unit Watchdog timer Analog comparator I/O Module 1 I/O Module 2 I/O Module n 33 ...
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... SPI, and other I/O functions. The I/O Memory can be accessed directly the Data Space locations following those of the Register File, 0x20 - 0x5F. In addition, the ATA6612/ATA6613 has Extended I/O space from 0x60 - 0xFF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used. ...
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... The S-bit is always an exclusive or between the Negative Flag N and the Two’s Comple- ment Overflow Flag V. See the “Instruction Set Description” for detailed information. 9111C–AUTO–02/ R/W R/W R/W R ATA6612/ATA6613 R/W R/W R/W R SREG 35 ...
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... Two 8-bit output operands and one 16-bit result input • One 16-bit output operand and one 16-bit result input Figure 6-3 Figure 6-3. General Purpose Working Registers ATA6612/ATA6613 36 shows the structure of the 32 general purpose working registers in the CPU. AVR CPU General Purpose Working Registers ...
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... Stack with return from subroutine RET or return from interrupt RETI. 9111C–AUTO–02/08 Figure 6-3 on page 36, each register is also assigned a data memory address, The X-, Y-, and Z-registers R27 (0x1B R29 (0x1D R31 (0x1F) ATA6612/ATA6613 Figure 6- R26 (0x1A R28 (0x1C R30 (0x1E ...
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... MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit. Figure 6-5. Figure 6-6 on page 39 cycle an ALU operation using two register operands is executed, and the result is stored back to the destination register. ATA6612/ATA6613 SP15 ...
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... The Reset Vector can also be moved to the start of the Boot Flash section by programming the BOOTRST Fuse (see and ATA6613” on page When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are dis- abled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – ...
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... A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set. ATA6612/ATA6613 40 ; store SREG value ; disable interrupts during timed sequence ...
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... Since all AVR instructions are bits wide, the Flash is organized as 2/4/8K x 16. For software security, the Flash Program memory space is divided into two sec- tions, Boot Loader Section and Application Program Section in ATA6612 and ATA6613. See SELFPRGEN description in section SPMCSR” ...
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... Figure 6-8. ATA6612/ATA6613 42 Program Memory Map, ATA6612/ATA6613 Program Memory Application Flash Section Boot Flash Section 0x0000 0x0FFF/0x1FFF 9111C–AUTO–02/08 ...
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... SRAM Data Memory Figure 6-9 The ATA6612/ATA6613 is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in the Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used. ...
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... EEPROM Data Memory The ATA6612/ATA6613 contains 512 bytes of data EEPROM memory organized as a sep- arate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register ...
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... Initial Value • Bits 7..6 – Res: Reserved Bits These bits are reserved bits in the ATA6612/ATA6613 and will always read as zero • Bits 5, 4 – EEPM1 and EEPM0: EEPROM Programming Mode Bits The EEPROM Programming mode bit setting defines which programming action that will be triggered when writing EEPE ...
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... Step 2 is only relevant if the software contains a Boot Loader allowing the CPU to pro- gram the Flash. If the Flash is never being updated by the CPU, step 2 can be omitted. See “Boot Loader Support – Read-While-Write Self-Programming, ATA6612 and ATA6613” on page 284 Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM Master Write Enable will time-out ...
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... Flash Boot Loader is present in the software. If such code is present, the EEPROM write function must also wait for any ongoing SPM command to finish. 9111C–AUTO–02/08 EEPROM Programming Time Number of Calibrated RC Oscillator Cycles 26,368 ATA6612/ATA6613 Table 6-3 lists the typical Typ Programming Time 3 ...
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... The next code examples show assembly and C functions for reading the EEPROM. The exam- ples assume that interrupts are controlled so that no interrupts will occur during execution of these functions. ATA6612/ATA6613 48 ; Wait for completion of previous write sbic EECR,EEPE rjmp EEPROM_write ; Set up address (r18:r17) in address register ...
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... Wait for completion of previous write */ while(EECR & (1<<EEPE Set up address register */ EEAR = uiAddress; /* Start eeprom read by writing EERE */ EECR |= (1<<EERE); /* Return data from Data Register */ return EEDR; the EEPROM data can be corrupted because the supply voltage is CC, ATA6612/ATA6613 reset Protection circuit can CC 49 ...
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... I/O Memory The I/O space definition of the ATA6612/ATA6613 is shown in 344. All ATA6612/ATA6613 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions ...
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... I/O Control Unit clk ASY System Clock Prescaler Source clock Clock Multiplexer Timer/Counter External Clock Oscillator is halted, TWI address recognition in all sleep modes. I/O ATA6612/ATA6613 CPU Core RAM ADC clk CPU clk FLASH Reset Logic Watchdog Timer Watchdog clock Watchdog Oscillator Crystal Low-frequency ...
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... Watchdog Oscillator and the number of cycles in the delay is set by the SUTx and CKSELx fuse bits. The selectable delays are shown in Watchdog Oscillator is voltage dependent as shown in ATA6612/ATA6613 52 ASY Device Clocking Options Select 1. For all fuses “1” means unprogrammed while “0” means programmed. ...
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... Number of Watchdog Oscillator Cycles = 5.0V) Typ Time-out ( 4 55. Table 6-6 on page C2 C1 54. ATA6612/ATA6613 = 3.0V) Number of Cycles 4 before it releases the reset, and the time-out delay CC Figure 6-12. Either a quartz crystal or a 54. For ceramic resonators, the capacitor val- XTAL2 ...
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... Ceramic resonator, slowly rising power Crystal Oscillator, BOD enabled Crystal Oscillator, fast rising power Crystal Oscillator, slowly rising power Notes: ATA6612/ATA6613 54 Low Power Crystal Oscillator Operating Modes (1) (MHz) CKSEL3..1 0.4 - 0.9 0.9 - 3.0 3.0 - 8.0 8.0 - 16.0 1. The frequency ranges are preliminary values. Actual values are TBD. ...
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... If 8 MHz frequency exceeds the specification of the device (depends on V Fuse can be programmed in order to divide the internal frequency must be ensured that the resulting divided clock meets the frequency specification of the device ATA6612/ATA6613 Figure 6-12 on page 53. Note that the Full Swing Crystal 56. For ceramic resonators, the capacitor val- Table ...
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... Table 6-10. Power Conditions BOD enabled Fast rising power Slowly rising power BOD enabled Fast rising power Slowly rising power Note: ATA6612/ATA6613 56 Start-up Times for the Full Swing Crystal Oscillator Clock Selection Start-up Time from Power-down and Power-save 258 CK 258 ...
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... Reserved 1. If the RSTDISBL fuse is programmed, this start-up time will be increased to 14CK + 4 ensure programming mode can be entered. The device is shipped with this option selected. 2. ATA6612/ATA6613 Table 6-11. If selected, it will operate with “Calibration Byte” (1)(3) CKSEL3..0 0010 ), the CKDIV8 ...
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... C. This clock may be select as the system clock by programming the CKSEL Fuses to “11” as shown in Table 6-13. Note: When this clock source is selected, start-up times are determined by the SUT Fuses as shown in Table 6-14 on page ATA6612/ATA6613 CAL7 CAL6 ...
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... NC EXTERNAL CLOCK SIGNAL Start-up Times for the External Clock Selection Start-up Time from Power-down and Power-save Reserved ATA6612/ATA6613 Additional Delay from Reset (1) 14CK 14CK + 4 ms 14CK + 64 ms Figure 6-14. To run the device on an Table 6-15. (2) ...
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... System Clock Prescaler The ATA6612/ATA6613 has a system clock prescaler, and the system clock can be divided by setting the decrease the system clock frequency and the power consumption when the requirement for pro- cessing power is low. This can be used with all clock source options, and it will affect the clock frequency of the CPU and all synchronous peripherals ...
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... The device is shipped with the CKDIV8 Fuse programmed. 9111C–AUTO–02/ CLKPCE – – – R Table 6-17 on page 62. ATA6612/ATA6613 CLKPS3 CLKPS2 CLKPS1 CLKPS0 R/W R/W R/W R/W See Bit Description CLKPR 61 ...
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... ATA6612/ATA6613, and their CLKPS0 Clock Division Factor Reserved 0 Reserved 1 Reserved 0 Reserved 1 Reserved 0 Reserved 1 Reserved Table 6-18 on page 63 for a summary enabled ...
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... Read/Write Initial Value • Bits 7..4 Res: Reserved Bits These bits are unused bits in the ATA6612/ATA6613, and will always read as zero. • Bits 3..1 – SM2..0: Sleep Mode Select Bits 2, 1, and 0 These bits select between the five available sleep modes as shown in Table 6-18. ...
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... If Timer/Counter2 is not using the asynchronous clock, the Timer/Counter Oscillator is stopped during sleep. If Timer/Counter2 is not using the synchronous clock, the clock source is stopped during sleep. Note that even if the synchronous clock is running in Power-save, this clock is only available for Timer/Counter2. ATA6612/ATA6613 64 , clk , and clk ...
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... Active Clock Domains (1) 1. Only recommended with external crystal or resonator selected as clock source Timer/Counter2 is running in asynchronous mode. 3. For INT1 and INT0, only level interrupt. “Power-down Supply Current” on page 330 ATA6612/ATA6613 Oscillators Wake-up Sources ( (2) (3) X ...
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... Timer/Counter0 is enabled, operation will continue like before the shutdown. • Bit 4 - Res: Reserved bit This bit is reserved in ATA6612/ATA6613 and will always read as zero. • Bit 3 - PRTIM1: Power Reduction Timer/Counter1 Writing a logic one to this bit shuts down the Timer/Counter1 module. When the Timer/Counter1 is enabled, operation will continue like before the shutdown. • ...
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... Comparator” on page 262 for details on the start-up time. “Watchdog Timer” on page 74 for details on how to configure the Watchdog Timer. ATA6612/ATA6613 “Analog-to-Digital Converter” on page 265 for details on how to configure the Analog “Brown-out Detection” on page 71 “Internal Volt- ...
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... During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. For the ATA6613, the instruction placed at the Reset Vector must be a JMP – Absolute Jump – instruction to the reset handling routine. For the ATA6612, the instruc- tion placed at the Reset Vector must be an RJMP – ...
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... Reset Sources The ATA6612/ATA6613 has four sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V • External Reset. The MCU is reset when a low level is present on the RESET pin for longer than the minimum pulse length. ...
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... PORMIN V VCC Rise Rate to ensure Power-on Reset CCRR V RESET Pin Threshold Voltage RST Note: 1. Before rising, the supply has to be between ATA6612/ATA6613 70 Table 6-20. The POR is activated whenever V rise. The RESET signal is activated again, without any delay, CC decreases below the detection level ...
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... V antees that a Brown-Out Reset will occur before V operation of the microcontroller is no longer guaranteed. The test is performed using BODLEVEL = 110 and BODLEVEL = 101 for ATA6612V/ATA6613V, and BODLEVEL = 101 ATA6612/ATA6613 and BODLEVEL = 101 for ATA6612/ATA6613 70) will generate a reset, even if the clock is not – ...
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... Time-out period t “Watchdog Timer” on page 74 Figure 6-20. Watchdog System Reset During Operation RESET TIME-OUT RESET TIME-OUT INTERNAL RESET ATA6612/ATA6613 72 Brown-out Characteristics Parameter Brown-out Detector Hysteresis Min Pulse Width on Brown-out Reset decreases to a value below the trigger level ( ...
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... Initial Value • Bit 7..4: Res: Reserved Bits These bits are unused bits in the ATA6612/ATA6613, and will always read as zero. • Bit 3 – WDRF: Watchdog System Reset Flag This bit is set if a Watchdog System Reset occurs. The bit is reset by a Power-on Reset writing a logic zero to the flag. • ...
Page 74
... Note: 6.8.9 Watchdog Timer ATA6612/ATA6613 has an Enhanced Watchdog Timer (WDT). The main features are: • Clocked from separate On-chip Oscillator • 3 Operating modes – Interrupt – System Reset – Interrupt and System Reset • Selectable Time-out period from • ...
Page 75
... WDCE bit cleared. This must be done in one operation. The following code example shows one assembly and one C function for turning off the Watch- dog Timer. The example assumes that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during the execution of these functions. 9111C–AUTO–02/08 ATA6612/ATA6613 75 ...
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... Assembly Code Example WDT_off: C Code Example void WDT_off(void Note: Note: ATA6612/ATA6613 76 (1) ; Turn off global interrupt cli ; Reset Watchdog Timer wdr ; Clear WDRF in MCUSR in r16, MCUSR andi r16, (0xff & (0<<WDRF)) MCUSR, r16 out ; Write logical one to WDCE and WDE ; Keep old prescaler setting to prevent unintentional time-out lds r16, WDTCSR r16, (1< ...
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... Finished setting new values, used 2 cycles - ; Turn on global interrupt sei ret (1) __disable_interrupt(); __watchdog_reset(); /* Start timed equence */ WDTCSR |= (1<<WDCE) | (1<<WDE); /* Set new prescaler(time-out) value = 64K cycles (~0 WDTCSR = (1<<WDE) | (1<<WDP2) | (1<<WDP0); __enable_interrupt(); 1. The example code assumes that the part specific header file is included. ATA6612/ATA6613 77 ...
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... Bit 3 - WDE: Watchdog System Reset Enable WDE is overridden by WDRF in MCUSR. This means that WDE is always set when WDRF is set. To clear WDE, WDRF must be cleared first. This feature ensures multiple resets dur- ing conditions causing failure, and a safe start-up after the failure. ATA6612/ATA6613 ...
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... The interrupt vectors in ATA6612 and ATA6613 are generally the same, with the following differences: • Each Interrupt Vector occupies two instruction words in ATA6613, and one instruction word in ATA6612. • In ATA6612 and ATA6613, the Reset Vector is affected by the BOOTRST fuse, and the Interrupt Vector start address is affected by the IVSEL bit in MCUCR. 9111C–AUTO–02/08 6-25. ...
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... When the BOOTRST Fuse is programmed, the device will jump to the Boot Loader address at reset (see “Boot Loader Support – Read-While-Write Self-Programming, ATA6612 and ATA6613” on page 284). 2. When the IVSEL bit in MCUCR is set, Interrupt Vectors will be moved to the start of the Boot Flash Section ...
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... SPH,r16 ldi r16, low(RAMEND) out SPL,r16 sei <instr> xxx ... ... ... ATA6612/ATA6613 (1) Interrupt Vectors Start Address 0x001 Boot Reset Address + 0x001 0x001 Boot Reset Address + 0x001 Table 6-107 on page 298. For the BOOTRST Fuse “1” Comments ; Reset Handler ; IRQ0 Handler ; IRQ1 Handler ...
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... Reset and Interrupt Vector Addresses in ATA6612 is: Address Labels Code .org 0x001 0x001 0x002 ... 0x019 ; .org 0xC00 0xC00 0xC01 0xC02 0xC03 0xC04 0xC05 ATA6612/ATA6613 82 RESET: ldi r16,high(RAMEND); Main program start out SPH,r16 ldi r16,low(RAMEND) out SPL,r16 sei <instr> xxx rjmp EXT_INT0 ...
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... Reset and Interrupt Vector Addresses in ATA6612 is: Address Labels Code ; .org 0xC00 0xC00 0xC01 0xC02 ... 0xC19 ; 0xC1A 0xC1B 0xC1C 0xC1D 0xC1E 0xC1F 6.9.2 Interrupt Vectors in ATA6613 Table 6-28. Reset and Interrupt Vectors in ATA6613 Program (2) Vector No. Address (1) 1 0x0000 2 0x0002 3 0x0004 4 0x0006 5 0x0008 6 0x000A 7 ...
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... When the IVSEL bit in MCUCR is set, Interrupt Vectors will be moved to the start of the Boot Flash Section. The address of each Interrupt Vector will then be the address in this table added to the start address of the Boot Flash Section. shows reset and Interrupt Vectors placement for the various combinations of Reset and Interrupt Vectors Placement in ATA6613 IVSEL Reset Address 1 ...
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... The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATA6613 is: Address Labels Code 0x0000 0x0002 0x0004 0x0006 0x0008 0x000A 0x000C 0x000E 0x0010 0x0012 0x0014 0x0016 0x0018 0x001A 0x001C 0x001E 0x0020 0x0022 0x0024 0x0026 0x0028 0x002A 0x002C ...
Page 86
... When the BOOTRST Fuse is programmed and the Boot section size set to 2K bytes, the most typical and general program setup for the Reset and Interrupt Vector Addresses in ATA6613 is: Address Labels Code .org 0x0002 0x0002 0x0004 ... ...
Page 87
... When the BOOTRST Fuse is programmed, the Boot section size set to 2K bytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses in ATA6613 is: Address Labels Code ...
Page 88
... The pin driver is strong enough to drive LED displays directly. All port pins have indi- vidually selectable pull-up resistors with a supply-voltage invariant resistance. All I/O pins have protection diodes to both V “Electrical Characteristics” on page 320 ATA6612/ATA6613 88 ; Enable change of Interrupt Vectors ldi r16, (1<<IVCE) out MCUCR, r16 ...
Page 89
... Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. 9111C–AUTO–02/08 Pxn C pin “Register Description for I/O Ports” on page 95. Refer to the individual module sections for a full description of the alter- ATA6612/ATA6613 R pu Logic See Figure "General Digital I/O" for Details 107. ...
Page 90
... If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero). ATA6612/ATA6613 90 (1) Pxn ...
Page 91
... Input 1 1 Input 0 X Output 1 X Output Figure 6-23 on page shows a timing diagram of the synchronization when reading an externally applied pin ATA6612/ATA6613 Pull-up Comment No Tri-state (Hi-Z) Yes Pxn will source current if ext. pulled low. No Tri-state (Hi-Z) No Output Low (Sink) No Output High (Source) 90, the PINxn Register bit and the preced- ...
Page 92
... When reading back a software assigned pin value, a nop instruction must be inserted as indi- cated in the clock. In this case, the delay tpd through the synchronizer is 1 system clock period. Figure 6-25. Synchronization when Reading a Software Assigned Pin Value ATA6612/ATA6613 92 SYSTEM CLK INSTRUCTIONS XXX ...
Page 93
... For the assembly program, two temporary registers are used to minimize the time from pull-ups are set on pins and 7, until the direction bits are correctly set, defining bit 2 and 3 as low and redefining bits 0 and 1 as strong high drivers. ATA6612/ATA6613 93 ...
Page 94
... In this case, the pull-up will be disabled during reset. If low power consumption during reset is important recommended to use an external pull-up or pull-down. Connecting unused pins directly to V accidentally configured as an output. ATA6612/ATA6613 94 Figure 6-23 on page 90, the digital input signal can be clamped to ground at the “Alternate Port Functions” on page ...
Page 95
... SLEEP CONTROL Pxn, PORT TOGGLE OVERRIDE ENABLE 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk SLEEP, and PUD are common to all ports. All other signals are unique for each pin. ATA6612/ATA6613 Figure 6-23 on page 90 PUD Q ...
Page 96
... The following subsections shortly describe the alternate functions for each port, and relate the overriding signals to the alternate function. Refer to the alternate function description for further details. ATA6612/ATA6613 96 summarizes the function of the overriding signals. The pin and port indexes from are not shown in the succeeding tables. The overriding signals are ...
Page 97
... SS (SPI Bus Master Slave select) OC1B (Timer/Counter1 Output Compare Match B Output) PCINT2 (Pin Change Interrupt 2) OC1A (Timer/Counter1 Output Compare Match A Output) PCINT1 (Pin Change Interrupt 1) ICP1 (Timer/Counter1 Input Capture Input) CLKO (Divided System Clock Output) PCINT0 (Pin Change Interrupt 0) ATA6612/ATA6613 – – IVSEL ...
Page 98
... SPI is enabled as a Slave, the data direction of this pin is controlled by DDB4. When the pin is forced by the SPI input, the pull-up can still be controlled by the PORTB4 bit. PCINT4: Pin Change Interrupt source 4. The PB4 pin can serve as an external interrupt source. ATA6612/ATA6613 98 9111C–AUTO–02/08 ...
Page 99
... Table 6-33 on page 100 to the overriding signals shown in SLAVE OUTPUT constitute the MISO signal, while MOSI is divided into SPI MSTR OUT- PUT and SPI SLAVE INPUT. 9111C–AUTO–02/08 ATA6612/ATA6613 and Table 6-34 on page 100 relate the alternate functions of Port B Figure 6-26 on page 95. SPI MSTR INPUT and SPI ...
Page 100
... DIEOV DI AIO Notes: Table 6-34. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO ATA6612/ATA6613 100 Overriding Signals for Alternate Functions in PB7..PB4 PB7/XTAL2/ PB6/XTAL1/ (1) TOSC2/PCINT7 TOSC1/PCINT6 INTRC • EXTCK+ INTRC + AS2 AS2 0 0 INTRC • EXTCK+ INTRC + AS2 AS2 0 ...
Page 101
... PCINT12 (Pin Change Interrupt 12) ADC3 (ADC Input Channel 3) PC3 PCINT11 (Pin Change Interrupt 11) ADC2 (ADC Input Channel 2) PC2 PCINT10 (Pin Change Interrupt 10) ADC1 (ADC Input Channel 1) PC1 PCINT9 (Pin Change Interrupt 9) ADC0 (ADC Input Channel 0) PC0 PCINT8 (Pin Change Interrupt 8) ATA6612/ATA6613 Table 6-35. 101 ...
Page 102
... PCINT9: Pin Change Interrupt source 9. The PC1 pin can serve as an external interrupt source. • ADC0/PCINT8 – Port C, Bit 0 PC0 can also be used as ADC input Channel 0. Note that ADC input channel 0 uses analog power. PCINT8: Pin Change Interrupt source 8. The PC0 pin can serve as an external interrupt source. ATA6612/ATA6613 102 9111C–AUTO–02/08 ...
Page 103
... PCINT11 • PCIE1 + PCINT10 • PCIE1 + ADC3D ADC2D PCINT11 • PCIE1 PCINT10 • PCIE1 PCINT11 INPUT PCINT10 INPUT ADC3 INPUT ADC2 INPUT ATA6612/ATA6613 (1) PC4/SDA/ADC4/PCINT12 TWEN PORTC4 • PUD TWEN SDA_OUT TWEN 0 PCINT12 • PCIE1 + ADC4D PCINT12 • PCIE1 PCINT12 INPUT ...
Page 104
... The OC0A pin is also the output pin for the PWM mode timer function. PCINT22: Pin Change Interrupt source 22. The PD6 pin can serve as an external interrupt source. ATA6612/ATA6613 104 Port D Pins Alternate Functions Alternate Function AIN1 (Analog Comparator Negative Input) ...
Page 105
... DDD0. When the USART forces this pin input, the pull-up can still be controlled by the PORTD0 bit. PCINT16: Pin Change Interrupt source 16. The PD0 pin can serve as an external interrupt source. 9111C–AUTO–02/08 ATA6612/ATA6613 105 ...
Page 106
... DIEOV DI AIO Table 6-40. Signal Name PUOE PUO DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO ATA6612/ATA6613 106 and Table 6-40 relate the alternate functions of Port D to the overriding signals Figure 6-26 on page 95. Overriding Signals for Alternate Functions PD7..PD4 PD7/AIN1 PD6/AIN0/ /PCINT23 OC0A/PCINT22 ...
Page 107
... R R/W R/W R – PINC6 PINC5 PINC4 N/A N/A N PORTD7 PORTD6 PORTD5 PORTD4 R/W R/W R/W R ATA6612/ATA6613 PORTB3 PORTB2 PORTB1 PORTB0 R/W R/W R/W R DDB3 DDB2 DDB1 DDB0 R/W R/W R/W R PINB3 PINB2 PINB1 PINB0 ...
Page 108
... MCU to complete the wake-up to trigger the level interrupt. If the level disappears before the end of the Start-up Time, the MCU will still wake up, but no inter- rupt will be generated. The start-up time is defined by the SUT and CKSEL Fuses as described in “System Clock and Clock Options” on page ATA6612/ATA6613 108 ...
Page 109
... Initial Value • Bit 7..4 – Res: Reserved Bits These bits are unused bits in the ATA6612/ATA6613, and will always read as zero. • Bit 3, 2 – ISC11, ISC10: Interrupt Sense Control 1 Bit 1 and Bit 0 The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the cor- responding interrupt mask are set ...
Page 110
... Initial Value • Bit 7..2 – Res: Reserved Bits These bits are unused bits in the ATA6612/ATA6613, and will always read as zero. • Bit 1 – INT1: External Interrupt Request 1 Enable When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled ...
Page 111
... Initial Value • Bit 7..3 - Res: Reserved Bits These bits are unused bits in the ATA6612/ATA6613, and will always read as zero. • Bit 2 - PCIE2: Pin Change Interrupt Enable 2 When the PCIE2 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 2 is enabled ...
Page 112
... Read/Write Initial Value • Bit 7 – Res: Reserved Bit This bit is an unused bit in the ATA6612/ATA6613, and will always read as zero. • Bit 6..0 – PCINT14..8: Pin Change Enable Mask 14..8 Each PCINT14..8-bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT14..8 is set and the PCIE1 bit in PCICR is set, pin change interrupt is enabled on the corresponding I/O pin ...
Page 113
... Control Logic clk Direction TN Prescaler TOP BOTTOM = = 0 OCnA (Int.Req.) Waveform Generation Fixed OCnB TOP (Int.Req.) Value Waveform Generation TCCRnB ATA6612/ATA6613 Figure 6-27. The device-spe- “8-bit Timer/Counter Register Description” on must be written to zero to TOVn (Int.Req.) TOSC1 T/C Oscillator TOSC2 clk I/O OCnA OCnB 113 ...
Page 114
... The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the Clock Select logic which is controlled by the Clock Select (CS02:0) bits located in the Timer/Counter Control Register (TCCR0B). For details on clock sources and pres- caler (see ATA6612/ATA6613 114 Table 6-43 are also used extensively throughout the document. ...
Page 115
... Signalize that TCNT0 has reached maximum value. Signalize that TCNT0 has reached minimum value (zero). ). clk can be generated from an external or internal clock source present or not. A CPU write overrides (has priority over) all counter clear or T0 118). ATA6612/ATA6613 TOVn (Int.Req.) Clock Select Edge Detector clk Tn Control Logic ...
Page 116
... Force Output Compare (FOC0x) bit. Forcing compare match will not set the OCF0x Flag or reload/clear the timer, but the OC0x pin will be updated real compare match had occurred (the COM0x1:0 bits settings define whether the OC0x pin is set, cleared or toggled). ATA6612/ATA6613 116 shows a block diagram of the Output Compare unit. DATA BUS ...
Page 117
... OC0x Register, not the OC0x pin system reset occur, the OC0x Register is reset to “0”. Figure 6-30. Compare Match Output Unit, Schematic 9111C–AUTO–02/08 COMnx1 Waveform COMnx0 D Generator FOCnx D PORT D clk I/O ATA6612/ATA6613 Figure 6-30 shows a simplified Q 1 OCnx DDR OCnx Pin 117 ...
Page 118
... The Output Compare unit can be used to generate interrupts at some given time. Using the Out- put Compare to generate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time. ATA6612/ATA6613 118 “8-bit Timer/Counter Register Description” on page Table 6-44 on page “ ...
Page 119
... As for the Normal mode of operation, the TOV0 Flag is set in the same timer clock cycle that the counter counts from MAX to 0x00. 9111C–AUTO–02/08 TCNTn OCn (Toggle Period f clk_I/O ------------------------------------------------------ - N OCRnx ATA6612/ATA6613 Figure 6-31. The counter value (TCNT0) OCnx Interrupt Flag Set (COMnx1 OC0 119 ...
Page 120
... OC0x Register at the compare match between OCR0x and TCNT0, and clearing (or setting) the OC0x Register at the timer clock cycle the counter is cleared (changes from TOP to BOTTOM). ATA6612/ATA6613 120 Figure 6-32. The TCNT0 value is in the timing diagram shown as a his- ...
Page 121
... The small horizontal line marks on the TCNT0 slopes represent compare matches between OCR0x and TCNT0. 9111C–AUTO–02/08 f clk_I/O = -------------------- - N 256 122. The TCNT0 value is in the timing diagram shown as a histogram for ATA6612/ATA6613 = f /2 when OCR0A is set to zero. This OC0 clk_I/O 121 ...
Page 122
... PWM mode. If the OCR0A is set equal to BOTTOM, the output will be continuously low and if set equal to MAX the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values. ATA6612/ATA6613 122 1 ...
Page 123
... Timer/Counter operation. The figure clk I/O TN /1) MAX - 1 shows the same timing data, but with the prescaler enabled. I/O TN /8) MAX - 1 ATA6612/ATA6613 OCnx has a transition from high to low Figure 6-33 on page 122. When the OCR0A ) is therefore shown MAX BOTTOM /8) clk_I/O MAX ...
Page 124
... Figure 6-37 mode where OCR0A is TOP. Figure 6-37. Timer/Counter Timing Diagram, Clear Timer on Compare Match Mode, with Pres- clkTN (clk TCNTn (CTC) OCRnx OCFnx ATA6612/ATA6613 124 shows the setting of OCF0B in all modes and OCF0A in all modes except CTC I/O clk Tn /8) I/O OCRnx - 1 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode and fast PWM ...
Page 125
... Clear OC0A on Compare Match, set OC0A at TOP 1 Set OC0A on Compare Match, clear OC0A at TOP 1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the Com- pare Match is ignored, but the set or clear is done at TOP. See for more details. ATA6612/ATA6613 – ...
Page 126
... Table 6-48. COM0B1 Note: ATA6612/ATA6613 126 shows the COM0A1:0 bit functionality when the WGM02:0 bits are set to phase cor- Compare Output Mode, Phase Correct PWM Mode COM0A0 Description 0 Normal port operation, OC0A disconnected. WGM02 = 0: Normal Port Operation, OC0A Disconnected. ...
Page 127
... Note: • Bits 3, 2 – Res: Reserved Bits These bits are reserved bits in the ATA6612/ATA6613 and will always read as zero. • Bits 1:0 – WGM01:0: Waveform Generation Mode Combined with the WGM02 bit found in the TCCR0B Register, these bits control the count- ...
Page 128
... OCR0B as TOP. The FOC0B bit is always read as zero. • Bits 5:4 – Res: Reserved Bits These bits are reserved bits in the ATA6612/ATA6613 and will always read as zero. • Bit 3 – WGM02: Waveform Generation Mode See the description in the • Bits 2:0 – CS02:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter ...
Page 129
... External clock source on T0 pin. Clock on falling edge External clock source on T0 pin. Clock on rising edge R/W R/W R/W R R/W R/W R/W R R/W R/W R/W R ATA6612/ATA6613 TCNT0[7:0] R/W R/W R OCR0A[7:0] R/W R/W R OCR0B[7:0] R/W R/W R ...
Page 130
... Initial Value • Bits 7..3 – Res: Reserved Bits These bits are reserved bits in the ATA6612/ATA6613 and will always read as zero. • Bit 2 – OCIE0B: Timer/Counter Output Compare Match B Interrupt Enable When the OCIE0B bit is written to one, and the I-bit in the Status Register is set, the Timer/Counter Compare Match B interrupt is enabled ...
Page 131
... Alternatively, one of four taps from the prescaler can be used as a CLK_I/O ). The T1/T0 pin is sampled once every system clock cycle by the pin synchronization T0 shows a functional equivalent block diagram of the T1/T0 synchronization and /clk T1 ATA6612/ATA6613 Table 6-50 on page 127. /8, f CLK_I/O CLK_I/O pulse for each positive (CSn2 negative ...
Page 132
... Oscillator source (crystal, resonator, and capacitors) tolerances recommended that maximum frequency of an external clock source is less than f An external clock source can not be prescaled. Figure 6-39. Prescaler for Timer/Counter0 and Timer/Counter1 clk PSRSYNC CS10 CS11 CS12 Note: ATA6612/ATA6613 132 clk I/O Synchronization < ...
Page 133
... Timer/Counter1 module. 9111C–AUTO–02/ TSM – – – R 155. “Power Reduction Register - PRR” on page 66 ATA6612/ATA6613 – – PSRASY PSRSYNC R R R/W R Figure 6-40 on page “16-bit Timer/Counter Register must be written to zero to GTCCR 134 ...
Page 134
... T1 pin. The Clock Select logic block controls which clock source and edge the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select logic is referred to as the timer clock (clk ATA6612/ATA6613 134 Count ...
Page 135
... The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be one of the fixed values: 0x00FF, 0x01FF, or 0x03FF the value stored in the OCR1A or ICR1 Register. The assignment is depen- dent of the mode of operation. ATA6612/ATA6613 135 ...
Page 136
... The following code examples show how atomic read of the TCNT1 Register contents. Reading any of the OCR1A/B or ICR1 Registers can be done by using the same principle. ATA6612/ATA6613 136 (1) (1) 1. The example code assumes that the part specific header file is included. For I/O Registers located in extended I/O map, “ ...
Page 137
... For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. ATA6612/ATA6613 137 ...
Page 138
... If writing to more than one 16-bit register where the high byte is the same for all registers written, then the high byte only needs to be written once. However, note that the same rule of atomic operation described previously also applies in this case. ATA6612/ATA6613 138 (1) (1) 1 ...
Page 139
... Signalize that TCNT1 has reached minimum value (zero). ). The clk can be generated from an external or internal clock source present or not. A CPU write overrides (has priority over) all counter clear ATA6612/ATA6613 131). TOVn (Int.Req.) Clock Select Edge Detector clk Tn Control Logic ...
Page 140
... TCNT1 value is copied into ICR1 Register. If enabled (ICIE1 = 1), the Input Capture Flag generates an Input Capture interrupt. The ICF1 Flag is automatically cleared when the interrupt is executed. Alternatively the ICF1 Flag can be cleared by software by writing a logical one to its I/O bit location. ATA6612/ATA6613 140 “Modes of Operation” on page DATA BUS (8-bit) ...
Page 141
... Even though the Input Capture interrupt has relatively high priority, the maximum interrupt response time is dependent on the maximum number of clock cycles it takes to handle any of the other interrupt requests. 9111C–AUTO–02/08 135. ATA6612/ATA6613 “Accessing 16-bit Registers” Figure 6-38 on page 132). The edge detector is 141 ...
Page 142
... Compare unit (A/B). The elements of the block diagram that are not directly a part of the Output Compare unit are gray shaded. Figure 6-43. Output Compare Unit, Block Diagram ATA6612/ATA6613 142 “Modes of Operation” on page shows a block diagram of the Output Compare unit. The small “n” in the register and ...
Page 143
... Normal mode. The OC1x Register keeps its value even when changing between Waveform Generation modes. Be aware that the COM1x1:0 bits are not double buffered together with the compare value. Changing the COM1x1:0 bits will take effect immediately. 9111C–AUTO–02/08 135. ATA6612/ATA6613 “Accessing 16-bit Registers” 143 ...
Page 144
... The design of the Output Compare pin logic allows initialization of the OC1x state before the out- put is enabled. Note that some COM1x1:0 bit settings are reserved for certain modes of operation (see The COM1x1:0 bits have no effect on the Input Capture unit. ATA6612/ATA6613 144 COMnx1 Waveform ...
Page 145
... Output Compare to generate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time. 9111C–AUTO–02/08 Table 6-53 on page “Compare Match Output Unit” on page “Timer/Counter Timing Diagrams” on page ATA6612/ATA6613 155. For fast PWM mode refer to 144). Table 6-54 on Table 6-55 on 153. ...
Page 146
... OCnA The N variable represents the prescaler factor (1, 8, 64, 256, or 1024). As for the Normal mode of operation, the TOV1 Flag is set in the same timer clock cycle that the counter counts from MAX to 0x0000. ATA6612/ATA6613 146 TCNTn OCnA (Toggle ...
Page 147
... Figure 6-46. Fast PWM Mode, Timing Diagram 9111C–AUTO–02/08 TOP log + 1 = ---------------------------------- - log 2 TCNTn OCnx OCnx Period ATA6612/ATA6613 Figure OCRnx/TOP Update and TOVn Interrupt Flag Set and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) (COMnx1 (COMnx1 6-46. The figure 147 ...
Page 148
... PWM mode. If the OCR1x is set equal to BOTTOM (0x0000) the out- put will be a narrow spike for each TOP+1 timer clock cycle. Setting the OCR1x equal to TOP will result in a constant high or low output (depending on the polarity of the output set by the COM1x1:0 bits). ATA6612/ATA6613 148 f clk_I/O ...
Page 149
... TCNT1 slopes represent compare matches between OCR1x and TCNT1. The OC1x Interrupt Flag will be set when a compare match occurs. 9111C–AUTO–02/ when OCR1A is set to zero (0x0000). This feature clk_I/O TOP log ---------------------------------- - log 2 ATA6612/ATA6613 Figure 6-47 on page 149 ...
Page 150
... The PWM waveform is generated by setting (or clearing) the OC1x Register at the compare match between OCR1x and TCNT1 when the counter increments, and clearing (or setting) the OC1x Register at compare match between OCR1x and TCNT1 when the counter decrements. ATA6612/ATA6613 150 TCNTn OCnx ...
Page 151
... OCR1x and TCNT1. The OC1x Interrupt Flag will be set when a compare match occurs. 9111C–AUTO–02/08 f clk_I/O = --------------------------------- N TOP 2 and Figure 6-48 on page 152). TOP log + 1 = ---------------------------------- - log 2 Figure 6-48 on page ATA6612/ATA6613 Figure 6-47 152. The figure shows phase and fre- 151 ...
Page 152
... OC1x Register at compare match between OCR1x and TCNT1 when the counter decrements. The PWM frequency for the output when using phase and frequency correct PWM can be calculated by the following equation: f OCnxPFCPWM The N variable represents the prescaler divider (1, 8, 64, 256, or 1024). ATA6612/ATA6613 152 TCNTn OCnx OCnx 1 ...
Page 153
... OCRnx OCFnx shows the same timing data, but with the prescaler enabled. clk I/O clkTn (clk /8) I/O TCNTn OCRnx - 1 OCRnx OCFnx ATA6612/ATA6613 ) is therefore shown shows a timing diagram for the setting of OCF1x. OCRnx OCRnx + 1 OCRnx Value OCRnx OCRnx + 1 OCRnx Value OCRnx + 2 /8) clk_I/O ...
Page 154
... ICFn (if used (Update at TOP) Figure 6-52 Figure 6-52. Timer/Counter Timing Diagram, with Prescaler (f (CTC and FPWM) (PC and PFC PWM) TOVn (FPWM) and ICFn (if used (Update at TOP) ATA6612/ATA6613 154 shows the count sequence close to TOP in various modes. When using phase and clk I/O clk Tn (clk /1) ...
Page 155
... A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. In this case the compare match is ignored, but the set or clear is done at TOP. See Mode” on page 147 for more details. ATA6612/ATA6613 – – WGM11 R R/W ...
Page 156
... Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes (see of Operation” on page ATA6612/ATA6613 156 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the phase ...
Page 157
... CTC 0 1 (Reserved Fast PWM 1 1 Fast PWM ICNC1 ICES1 – R/W R ATA6612/ATA6613 Update of TOP OCR1 0xFFFF Immediate 0x00FF TOP 0x01FF TOP 0x03FF TOP OCR1A Immediate 0x00FF TOP 0x01FF TOP 0x03FF TOP ICR1 BOTTOM OCR1A BOTTOM ICR1 ...
Page 158
... COM1x1:0 bits that determine the effect of the forced compare. A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare match (CTC) mode using OCR1A as TOP. The FOC1A/FOC1B bits are always read as zero. ATA6612/ATA6613 158 and Figure 6-50 on page ...
Page 159
... TCNT1[15:8] TCNT1[7:0] R/W R/W R/W R 135 OCR1A[15:8] OCR1A[7:0] R/W R/W R/W R OCR1B[15:8] OCR1B[7:0] R/W R/W R/W R “Accessing 16-bit Registers” on page ATA6612/ATA6613 R/W R/W R/W R “Accessing 16-bit R/W R/W R/W R R/W R/W R/W R 135). TCNT1H TCNT1L OCR1AH ...
Page 160
... Initial Value • Bit 7, 6 – Res: Reserved Bits These bits are unused bits in the ATA6612/ATA6613, and will always read as zero. • Bit 5 – ICIE1: Timer/Counter1, Input Capture Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Input Capture interrupt is enabled ...
Page 161
... Initial Value • Bit 7, 6 – Res: Reserved Bits These bits are unused bits in the ATA6612/ATA6613, and will always read as zero. • Bit 5 – ICF1: Timer/Counter1, Input Capture Flag This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Reg- ister (ICR1) is set by the WGM13 used as the TOP value, the ICF1 Flag is set when the counter reaches the TOP value ...
Page 162
... I/O Register and bit locations are listed in the page 174. The PRTIM2 bit in enable Timer/Counter2 module. Figure 6-53. 8-bit Timer/Counter Block Diagram Timer/Counter TCNTn = OCRnA = OCRnB TCCRnA ATA6612/ATA6613 162 “Power Reduction Register - PRR” on page 66 Count Clear Control Logic clk Direction TN Prescaler TOP BOTTOM = ...
Page 163
... OCR2A Register. The assignment is dependent on the mode of operation default equal to the MCU clock, clk T2 181). For details on clock sources and prescaler, 183. ATA6612/ATA6613 for details. The compare match event will also . When the AS2 I/O “Asyn- 163 ...
Page 164
... For more details about advanced counting sequences and waveform generation (see Operation” on page The Timer/Counter Overflow Flag (TOV2) is set according to the mode of operation selected by the WGM22:0 bits. TOV2 can be used for generating a CPU interrupt. ATA6612/ATA6613 164 DATA BUS count clear ...
Page 165
... COM2x1:0 bits settings define whether the OC2x pin is set, cleared or toggled). 9111C–AUTO–02/08 shows a block diagram of the Output Compare unit. DATA BUS OCRnx = (8-bit Comparator) top bottom Waveform Generator FOCn WGMn1:0 ATA6612/ATA6613 “Modes of Operation” on page TCNTn OCFnx (Int.Req.) OCnx COMnX1:0 165 ...
Page 166
... I/O pins in the figure are shown in bold. Only the parts of the general I/O Port Control Registers (DDR and PORT) that are affected by the COM2x1:0 bits are shown. When referring to the OC2x state, the reference is for the internal OC2x Register, not the OC2x pin. ATA6612/ATA6613 166 Figure 6-56 on page 167 shows a 9111C– ...
Page 167
... For non-PWM modes, the action can be forced to have immediate effect by using the FOC2x strobe bits. 9111C–AUTO–02/08 COMnx1 Waveform COMnx0 Generator FOCnx clk I/O “8-bit Timer/Counter Register Description” on page Table 6-61 on page ATA6612/ATA6613 OCnx PORT D Q DDR 174) ...
Page 168
... The timing diagram for the CTC mode is shown in increases until a compare match occurs between TCNT2 and OCR2A, and then counter (TCNT2) is cleared. Figure 6-57. CTC Mode, Timing Diagram ATA6612/ATA6613 168 “Compare Match Output Unit” on page “Timer/Counter Timing Diagrams” on page TCNTn ...
Page 169
... PWM outputs. The small horizontal line marks on the TCNT2 slopes represent compare matches between OCR2x and TCNT2. 9111C–AUTO–02/08 f clk_I/O ------------------------------------------------------ - N OCRnx TOV2 Figure 6-58 on page ATA6612/ATA6613 Flag is set in the same timer clock cycle that the 170. The TCNT2 value is in the timing diagram = OC2A 169 ...
Page 170
... OC2x to toggle its logical level on each compare match (COM2x1:0 = 1). The waveform generated will have a maximum frequency of f ture is similar to the OC2A toggle in CTC mode, except the double buffer feature of the Output Compare unit is enabled in the fast PWM mode. ATA6612/ATA6613 170 1 2 ...
Page 171
... The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches BOTTOM. The Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM value. 9111C–AUTO–02/08 6-59. The TCNT2 value is in the timing diagram shown as a histogram for illustrating 1 ATA6612/ATA6613 OCnx Interrupt OCRnx Update TOVn Interrupt (COMnx1 (COMnx1 ...
Page 172
... Figure 6-60 count sequence close to the MAX value in all modes other than phase correct PWM mode. Figure 6-60. Timer/Counter Timing Diagram, no Prescaling clk (clk I/O TCNTn TOVn ATA6612/ATA6613 172 f clk_I/O = -------------------- - N 510 Figure 6-59 on page 171 contains timing data for basic Timer/Counter operation. The figure shows the ...
Page 173
... OCF2A in all modes except CTC mode. clk I/O clk Tn /8) I/O OCRnx - 1 shows the setting of OCF2A and the clearing of TCNT2 in CTC mode. caler (f /8) clk_I/O clk I/O clkTN /8) I/O TOP - 1 ATA6612/ATA6613 /8) clk_I/O MAX BOTTOM OCRnx OCRnx + 1 OCRnx Value TOP BOTTOM TOP BOTTOM + 1 /8) clk_I/O OCRnx + 2 BOTTOM + 1 173 ...
Page 174
... CTC mode (non-PWM). Table 6-58. COM2A1 Table 6-59 mode. Table 6-59. COM2A1 Note: ATA6612/ATA6613 174 COM2A1 COM2A0 COM2B1 COM2B0 R/W R/W R Table 6-58 shows the COM2A1:0 bit functionality when the WGM22:0 Compare Output Mode, non-PWM Mode COM2A0 ...
Page 175
... A special case occurs when OCR2B equals TOP and COM2B1 is set. In this case, the Com- pare Match is ignored, but the set or clear is done at TOP. See page 171 for more details. ATA6612/ATA6613 (1) “Phase Correct PWM Mode” on (1) “Phase Correct PWM Mode” on ...
Page 176
... Note: • Bits 3, 2 – Res: Reserved Bits These bits are reserved bits in the ATA6612/ATA6613 and will always read as zero. • Bits 1:0 – WGM21:0: Waveform Generation Mode Combined with the WGM22 bit found in the TCCR2B Register, these bits control the counting ...
Page 177
... OCR2B as TOP. The FOC2B bit is always read as zero. • Bits 5:4 – Res: Reserved Bits These bits are reserved bits in the ATA6612/ATA6613 and will always read as zero. • Bit 3 – WGM22: Waveform Generation Mode See the description in • Bit 2:0 – CS22:0: Clock Select ...
Page 178
... Read/Write Initial Value The Output Compare Register B contains an 8-bit value that is continuously compared with the counter value (TCNT2). A match can be used to generate an Output Compare interrupt generate a waveform output on the OC2B pin. ATA6612/ATA6613 178 Clock Select Bit Description CS21 CS20 Description ...
Page 179
... – – – – ATA6612/ATA6613 – OCIE2B OCIE2A TOIE2 R R/W R/W R – OCF2B OCF2A TOV2 R R/W R/W R TIMSK2 ...
Page 180
... TOSC1 cycle, the interrupt will not occur, and the device will fail to wake up. If the user is in doubt whether the time before re-entering Power-save or ADC Noise Reduction mode is sufficient, the following algorithm can be used to ensure that one TOSC1 cycle has elapsed: ATA6612/ATA6613 180 TCR2xUB. Enable interrupts, if needed. ...
Page 181
... Note that the crystal Oscillator will only run when this bit is zero. 9111C–AUTO–02/08 ) again becomes active, TCNT2 will read as the previous value (before entering I – EXCLK AS2 TCN2UB OCR2AUB R R/W R ATA6612/ATA6613 OCR2BUB TCR2AUB TCR2BUB ASSR R 0 181 ...
Page 182
... The mechanisms for reading TCNT2, OCR2A, OCR2B, TCCR2A and TCCR2B are differ- ent. When reading TCNT2, the actual timer value is read. When reading OCR2A, OCR2B, TCCR2A and TCCR2B the value in the temporary storage register is read. ATA6612/ATA6613 182 9111C–AUTO–02/08 ...
Page 183
... Additionally, clk T2S T2S TSM – – – R ATA6612/ATA6613 10-BIT T/C PRESCALER 0 clk T2 . clk is by default connected to the main T2S T2S /8, clk /32, clk T2S T2S as well as 0 (stop) may be selected. T2S – ...
Page 184
... Serial Peripheral Interface – SPI The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATA6612/ATA6613 and peripheral devices or between several AVR devices. The ATA6612/ATA6613 SPI includes the following features: • Full-duplex, Three-wire Synchronous Data Transfer • Master or Slave Operation • ...
Page 185
... SPI Data Register before the next character has been completely shifted in. Oth- erwise, the first byte is lost. 9111C–AUTO–02/08 MASTER LSB MSB 8 BIT SHIFT REGISTER SPI CLOCK GENERATOR ATA6612/ATA6613 Figure MSB SLAVE MISO MISO 8 BIT SHIFT REGISTER MOSI MOSI SHIFT ENABLE ...
Page 186
... Register controlling the SPI pins. DD_MOSI, DD_MISO and DD_SCK must be replaced by the actual data direction bits for these pins. E.g. if MOSI is placed on pin PB5, replace DD_MOSI with DDB5 and DDR_SPI with DDRB. ATA6612/ATA6613 186 Table 6-66. For more details on automatic port overrides, refer to 95 ...
Page 187
... Start transmission */ SPDR = cData; /* Wait for transmission complete */ while(!(SPSR & (1<<SPIF))) } Note: 9111C–AUTO–02/08 (1) r17,(1<<DD_MOSI)|(1<<DD_SCK) DDR_SPI,r17 r17,(1<<SPE)|(1<<MSTR)|(1<<SPR0) SPCR,r17 SPDR,r16 ( The example code assumes that the part specific header file is included. ATA6612/ATA6613 187 ...
Page 188
... Enable SPI */ SPCR = (1<<SPE); } char SPI_SlaveReceive(void Wait for reception complete */ while(!(SPSR & (1<<SPIF))) /* Return Data Register */ return SPDR; } Note: ATA6612/ATA6613 188 (1) r17,(1<<DD_MISO) DDR_SPI,r17 r17,(1<<SPE) SPCR,r17 r16,SPDR ( The example code assumes that the part specific header file is included. ...
Page 189
... When the DORD bit is written to one, the LSB of the data word is transmitted first. When the DORD bit is written to zero, the MSB of the data word is transmitted first. 9111C–AUTO–02/ SPIE SPE DORD MSTR CPOL R/W R/W R/W R/W R ATA6612/ATA6613 CPHA SPR1 SPR0 SPCR R/W R/W R 189 ...
Page 190
... Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0 These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have no effect on the Slave. The relationship between SCK and the Oscillator Clock fre- quency f Table 6-69. SPI2X ATA6612/ATA6613 190 Figure 6-67 and CPOL Functionality CPOL ...
Page 191
... SPI Data Register. • Bit 5..1 – Res: Reserved Bits These bits are reserved bits in the ATA6612/ATA6613 and will always read as zero. • Bit 0 – SPI2X: Double SPI Speed Bit When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI is in Master mode (see period will be two CPU clock periods ...
Page 192
... Table 6-70. CPOL=0, CPHA=0 CPOL=0, CPHA=1 CPOL=1, CPHA=0 CPOL=1, CPHA=1 Figure 6-67. SPI Transfer Format with CPHA = 0 Figure 6-68. SPI Transfer Format with CPHA = 1 ATA6612/ATA6613 192 Figure 6-68. Data bits are shifted out and latched in on opposite edges of the SCK sig- and Table 6-68, as done below. ...
Page 193
... Overview A simplified block diagram of the USART Transmitter is shown in accessible I/O Registers and I/O pins are shown in bold. 9111C–AUTO–02/08 ATA6612/ATA6613 “USART in SPI Mode” on page “Power Reduction Register - PRR” on page 66 Figure 6-69 on page 220. The 194. CPU ...
Page 194
... The recovery units are used for asynchronous data reception. In addition to the recovery units, the Receiver includes a Parity Checker, Control logic, a Shift Register and a two level receive buffer (UDRn). The Receiver supports the same frame formats as the Transmitter, and can detect Frame Error, Data OverRun and Parity Errors. ATA6612/ATA6613 194 (1) UBRRn [H:L] ...
Page 195
... Transmitter clock (Internal Signal). Receiver base clock (Internal Signal). Input from XCK pin (internal Signal). Used for synchronous slave operation. Clock output to XCK pin (Internal Signal). Used for synchronous master operation. XTAL pin frequency (System Clock). ATA6612/ATA6613 U2Xn / DDR_XCKn ...
Page 196
... For the Transmitter, there are no downsides. ATA6612/ATA6613 196 contains equations for calculating the baud rate (in bits per second) and for calculat- ...
Page 197
... Figure 6-70 on page 195 f OSC ---------- - 4 depends on the stability of the system clock source therefore recommended to osc UCPOL = 1 XCK RxD / TxD UCPOL = 0 XCK RxD / TxD Figure 6-71 shows, when UCPOLn is zero the data will be changed at ATA6612/ATA6613 for details. Sample Sample 197 ...
Page 198
... USART Stop Bit Select (USBSn) bit. The Receiver ignores the second stop bit (Frame Error) will therefore only be detected in the cases where the first stop bit is zero. ATA6612/ATA6613 198 illustrates the possible combinations of the frame formats. Bits inside brackets are ...
Page 199
... For the assembly code, the baud rate parameter is assumed to be stored in the r17:r16 Registers. 9111C–AUTO–02/ even n 1 – odd n 1 – Parity bit using even parity even odd Parity bit using odd parity Data bit n of the character n ATA6612/ATA6613 199 ...
Page 200
... However, many applications use a fixed setting of the baud and control registers, and for these types of applications the initialization code can be placed directly in the main routine combined with initialization code for other I/O modules. ATA6612/ATA6613 200 (1) UBRRnH, r17 UBRRnL, r16 r16, (1< ...