ATA6613 ATMEL Corporation, ATA6613 Datasheet - Page 51

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ATA6613

Manufacturer Part Number
ATA6613
Description
Ata6613
Manufacturer
ATMEL Corporation
Datasheet

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6.6
6.6.1
6.6.1.1
6.6.1.2
6.6.1.3
9111C–AUTO–02/08
System Clock and Clock Options
Clock Systems and their Distribution
CPU Clock – clk
I/O Clock – clk
Flash Clock – clk
Figure 6-11
clocks need not be active at a given time. In order to reduce power consumption, the clocks to
modules not being used can be halted by using different sleep modes, as described in
Management and Sleep Modes” on page
Figure 6-11. Clock Distribution
The CPU clock is routed to parts of the system concerned with operation of the AVR core.
Examples of such modules are the General Purpose Register File, the Status Register and the
data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing
general operations and calculations.
The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, and USART.
The I/O clock is also used by the External Interrupt module, but note that some external inter-
rupts are detected by asynchronous logic, allowing such interrupts to be detected even if the I/O
clock is halted. Also note that start condition detection in the USI module is carried out asynchro-
nously when clk
The Flash clock controls operation of the Flash interface. The Flash clock is usually active simul-
taneously with the CPU clock.
I/O
CPU
FLASH
Timer/Counter
Timer/Counter
Asynchronous
Oscillator
presents the principal clock systems in the AVR and their distribution. All of the
I/O
is halted, TWI address recognition in all sleep modes.
General I/O
Modules
External Clock
clk
clk
I/O
ASY
System Clock
Control Unit
AVR Clock
Multiplexer
Prescaler
Clock
ADC
62. The clock systems are detailed below.
Source clock
clk
Oscillator
ADC
Crystal
CPU Core
clk
clk
Reset Logic
CPU
FLASH
Crystal Oscillator
Watchdog clock
Low-frequency
ATA6612/ATA6613
Watchdog Timer
RAM
Watchdog
Oscillator
Calibrated RC
Flash and
EEPROM
Oscillator
“Power
51

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