ATA6613 ATMEL Corporation, ATA6613 Datasheet - Page 63

• Manufacturer Part Number: ATA6613
• Description: Ata6613
• Manufacturer: ATMEL Corporation

6.7.1
6.7.2
9111C–AUTO–02/08
Sleep Mode Control Register – SMCR
Idle Mode
The Sleep Mode Control Register contains control bits for power management.
Table 6-18.
Note:
When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle
mode, stopping the CPU but allowing the SPI, USART, Analog Comparator, ADC, 2-wire Serial
Interface, Timer/Counters, Watchdog, and the interrupt system to continue operating. This sleep
mode basically halts clk
Idle mode enables the MCU to wake up from external triggered interrupts as well as internal
ones like the Timer Overflow and USART Transmit Complete interrupts. If wake-up from the
Analog Comparator interrupt is not required, the Analog Comparator can be powered down by
setting the ACD bit in the Analog Comparator Control and Status Register – ACSR. This will
reduce power consumption in Idle mode. If the ADC is enabled, a conversion starts automati-
cally when this mode is entered.
• Bits 7..4 Res: Reserved Bits
• Bits 3..1 – SM2..0: Sleep Mode Select Bits 2, 1, and 0
• Bit 0 – SE: Sleep Enable
Initial Value
Read/Write
These bits are unused bits in the ATA6612/ATA6613, and will always read as zero.
These bits select between the five available sleep modes as shown in
The SE bit must be written to logic one to make the MCU enter the sleep mode when the
SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it is the
programmer’s purpose, it is recommended to write the Sleep Enable (SE) bit to one just
before the execution of the SLEEP instruction and to clear it immediately after waking up.
SM2
Bit
0
0
0
0
1
1
1
1
1. Standby mode is only recommended for use with external crystals or resonators.
Sleep Mode Select
R
7
–
0
SM1
0
0
1
1
0
0
1
1
CPU
R
6
–
0
and clk
FLASH
R
5
–
0
SM0
0
1
0
1
0
1
0
1
, while allowing the other clocks to run.
R
4
–
0
Sleep Mode
Idle
ADC Noise Reduction
Power-down
Power-save
Reserved
Reserved
Standby
Reserved
SM2
R/W
3
0
(1)
ATA6612/ATA6613
SM1
R/W
2
0
SM0
R/W
1
0
Table
R/W
SE
0
0
6-18.
SMCR
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