ATA6613 ATMEL Corporation, ATA6613 Datasheet - Page 153

• Manufacturer Part Number: ATA6613
• Description: Ata6613
• Manufacturer: ATMEL Corporation

6.14.9
9111C–AUTO–02/08
Timer/Counter Timing Diagrams
The extreme values for the OCR1x Register represents special cases when generating a PWM
waveform output in the phase correct PWM mode. If the OCR1x is set equal to BOTTOM the
output will be continuously low and if set equal to TOP the output will be set to high for
non-inverted PWM mode. For inverted PWM the output will have the opposite logic values. If
OCR1A is used to define the TOP value (WGM13:0 = 9) and COM1A1:0 = 1, the OC1A output
will toggle with a 50% duty cycle.
The Timer/Counter is a synchronous design and the timer clock (clk
clock enable signal in the following figures. The figures include information on when Interrupt
Flags are set, and when the OCR1x Register is updated with the OCR1x buffer value (only for
modes utilizing double buffering).
Figure 6-49. Timer/Counter Timing Diagram, Setting of OCF1x, no Prescaling
Figure 6-50
Figure 6-50. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (f
(clk
(clk
TCNTn
OCRnx
OCFnx
TCNTn
OCRnx
OCFnx
clkTn
clkTn
clk
I/O
clk
I/O
/1)
/8)
I/O
I/O
shows the same timing data, but with the prescaler enabled.
OCRnx - 1
OCRnx - 1
Figure 6-49
OCRnx
OCRnx
shows a timing diagram for the setting of OCF1x.
OCRnx Value
OCRnx Value
OCRnx + 1
ATA6612/ATA6613
OCRnx + 1
T1
) is therefore shown as a
OCRnx + 2
OCRnx + 2
clk_I/O
/8)
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