ATA6613 ATMEL Corporation, ATA6613 Datasheet - Page 110

• Manufacturer Part Number: ATA6613
• Description: Ata6613
• Manufacturer: ATMEL Corporation

6.11.2
6.11.3
110
ATA6612/ATA6613
External Interrupt Mask Register – EIMSK
External Interrupt Flag Register – EIFR
• Bit 7..2 – Res: Reserved Bits
• Bit 1 – INT1: External Interrupt Request 1 Enable
• Bit 0 – INT0: External Interrupt Request 0 Enable
• Bit 7..2 – Res: Reserved Bits
• Bit 1 – INTF1: External Interrupt Flag 1
• Bit 0 – INTF0: External Interrupt Flag 0
Initial Value
Initial Value
Read/Write
Read/Write
These bits are unused bits in the ATA6612/ATA6613, and will always read as zero.
When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the
external pin interrupt is enabled. The Interrupt Sense Control1 bits 1/0 (ISC11 and ISC10) in
the External Interrupt Control Register A (EICRA) define whether the external interrupt is
activated on rising and/or falling edge of the INT1 pin or level sensed. Activity on the pin will
cause an interrupt request even if INT1 is configured as an output. The corresponding inter-
rupt of External Interrupt Request 1 is executed from the INT1 Interrupt Vector.
When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the
external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in
the External Interrupt Control Register A (EICRA) define whether the external interrupt is
activated on rising and/or falling edge of the INT0 pin or level sensed. Activity on the pin will
cause an interrupt request even if INT0 is configured as an output. The corresponding inter-
rupt of External Interrupt Request 0 is executed from the INT0 Interrupt Vector.
These bits are unused bits in the ATA6612/ATA6613, and will always read as zero.
When an edge or logic change on the INT1 pin triggers an interrupt request, INTF1 becomes
set (one). If the I-bit in SREG and the INT1 bit in EIMSK are set (one), the MCU will jump to
the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is exe-
cuted. Alternatively, the flag can be cleared by writing a logical one to it. This flag is always
cleared when INT1 is configured as a level interrupt.
When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes
set (one). If the I-bit in SREG and the INT0 bit in EIMSK are set (one), the MCU will jump to
the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is exe-
cuted. Alternatively, the flag can be cleared by writing a logical one to it. This flag is always
cleared when INT0 is configured as a level interrupt.
Bit
Bit
R
R
7
–
0
7
–
0
R
R
6
–
0
6
–
0
R
R
5
–
0
5
–
0
R
R
4
–
0
4
–
0
R
R
3
–
0
3
–
0
R
R
2
–
0
2
–
0
INTF1
INT1
R/W
R/W
1
0
1
0
INTF0
INT0
R/W
R/W
9111C–AUTO–02/08
0
0
0
0
EIMSK
EIFR