XC3S502 Xilinx Corp., XC3S502 Datasheet - Page 170
![no-image](/images/no-image-200.jpg)
XC3S502
Manufacturer Part Number
XC3S502
Description
Spartan-3 Fpga Family Complete Data Sheet
Manufacturer
Xilinx Corp.
Datasheet
1.XC3S502.pdf
(208 pages)
- Current page: 170 of 208
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Spartan-3 FPGA Family: Pinout Descriptions
Table 102: FG676 Package Pinout (Continued)
Table 103: User I/Os Per Bank for XC3S1000 in FG676 Package
170
Bank
VCC
AUX
VCC
AUX
VCC
AUX
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Bottom
Edge
Right
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
CCLK
DONE
HSWAP_EN
Left
Top
XC3S1000
Pin Name
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
CCLK
DONE
HSWAP_EN
XC3S1500
Pin Name
Bank
I/O
0
1
2
3
4
5
6
7
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
CCLK
DONE
HSWAP_EN
XC3S2000
XC3S4000
Pin Name
Maximum
I/O
49
50
48
48
50
50
48
48
Number
FG676
AD26
AC24
W19
V26
H19
K10
K17
K18
U10
U17
U18
V10
V17
V18
Pin
J10
J17
J18
W8
V1
H8
K9
U9
V9
C2
J9
I/O
VCCAUX
VCCAUX
40
41
41
41
35
35
41
41
CONFIG
CONFIG
CONFIG
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
Type
www.xilinx.com
Table 102: FG676 Package Pinout (Continued)
User I/Os by Bank
Table 103
tributed between the eight I/O banks for the XC3S1000 in
the FG676 package. Similarly,
available user-I/O pins are distributed between the eight I/O
banks for the XC3S1500 in the FG676 package. Finally,
Table 105
and XC3S4000 in the FG676 package.
Notes:
1.
2.
DUAL
Bank
VCC
AUX
VCC
AUX
VCC
AUX
VCC
AUX
VCC
AUX
VCC
AUX
VCC
AUX
VCC
AUX
0
0
0
0
6
6
0
0
XC3S1500 balls D25 and F25 are not VREF pins although they are
designated as such. If a design uses an IOSTANDARD requiring
VREF in bank 2 then apply the workaround in
20519
XC3S4000 is pin compatible but uses alternate differential pairs on
six package balls.
All Possible I/O Pins by Type
M0
M1
M2
PROG_B
TCK
TDI
TDO
TMS
XC3S1000
Pin Name
.
indicates how the available user-I/O pins are dis-
shows the same information for the XC3S2000
DCI
2
2
2
2
2
2
2
2
M0
M1
M2
PROG_B
TCK
TDI
TDO
TMS
XC3S1500
Pin Name
M0
M1
M2
PROG_B
TCK
TDI
TDO
TMS
VREF
XC3S2000
XC3S4000
Pin Name
Table 104
DS099-4 (v2.2) May 25, 2007
5
5
5
5
5
5
5
5
Product Specification
Answer Record
Number
shows how the
FG676
AE3
AC3
AF3
B24
D24
A24
Pin
D3
C1
GCLK
2
2
0
0
2
2
0
0
CONFIG
CONFIG
CONFIG
CONFIG
JTAG
JTAG
JTAG
JTAG
Type
R
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