XC3S502 Xilinx Corp., XC3S502 Datasheet - Page 72
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XC3S502
Manufacturer Part Number
XC3S502
Description
Spartan-3 Fpga Family Complete Data Sheet
Manufacturer
Xilinx Corp.
Datasheet
1.XC3S502.pdf
(208 pages)
- Current page: 72 of 208
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Spartan-3 FPGA Family: DC and Switching Characteristics
Table 44: Timing for the IOB Output Path
72
Notes:
1.
2.
Clock-to-Output Times
Propagation Times
Set/Reset Times
T
Symbol
The numbers in this table are tested using the methodology presented in
forth in
This time requires adjustment whenever a signal standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned
to the data Output. When this is true, add the appropriate Output adjustment from
T
T
T
T
IOGSRQ
IOCKP
IOOLP
IOSRP
IOOP
Table 31
When reading from the
Output Flip-Flop (OFF), the
time from the active transition
at the OTCLK input to data
appearing at the Output pin
The time it takes for data to
travel from the IOB’s O input
to the Output pin
The time it takes for data to
travel from the O input
through the OFF latch to the
Output pin
Time from asserting the
OFF’s SR input to
setting/resetting data at the
Output pin
Time from asserting the
Global Set Reset (GSR) net
to setting/resetting data at
the Output pin
and
Table
Description
34.
LVCMOS25
output drive, Fast slew
rate
LVCMOS25
output drive, Fast slew
rate
LVCMOS25
output drive, Fast slew
rate
www.xilinx.com
Conditions
(2)
(2)
(2)
, 12mA
, 12mA
, 12mA
Table 47
XC3S200
XC3S400
XC3S50
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
XC3S200
XC3S400
XC3S50
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
XC3S200
XC3S400
XC3S50
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
XC3S200
XC3S400
XC3S50
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
Device
Table
and are based on the operating conditions set
All
46.
0.49
0.73
0.49
0.73
0.49
0.73
0.80
1.04
3.07
Min
-0
Speed Grade
DS099-3 (v2.2) May 25, 2007
Max
1.28
1.95
1.28
1.94
1.28
1.95
2.10
2.77
8.07
-5
Product Specification
Max
1.47
2.24
1.46
2.23
1.47
2.24
2.41
3.18
9.28
-4
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
R
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