L9803 STMicroelectronics, L9803 Datasheet
L9803
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L9803 Summary of contents
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... Instructions and 17 main Addressing Modes ■ Unsigned Multiply Instruction ■ True Bit Manipulation ■ Complete Development Support on DOS/WINDOWS ■ Full Software Package on DOS/WINDOWS™ (C-Compiler, Cross-Assembler, Debugger). Package HiQUAD64 Rev 1 L9803 HiQUAD64 Real-Time Emulator TM Packing Tray 1/126 www.st.com 1 ...
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... Miscellaneous Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.5 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.5.1 3.5.2 3.5.3 3.5.4 3.6 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.7 Power Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.7.1 3.7.2 3.7.3 3.7.4 2/126 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Dedicated Control Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Power-on Reset - Low Voltage Detection . . . . . . . . . . . . . . . . . . . . . . . 25 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Slow Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 L9803 ...
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... L9803 4 Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.1.1 4.2 Digital Section Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.2.1 4.3 Analog Section Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.3.1 5 On-Chip Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.1 I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.1.1 5.1.2 5.1.3 5.2 16-Bit Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.2.1 5.2.2 5.2.3 5.2.4 5.3 PWM Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 5.3.1 5.3.2 5.3.3 5.4 PWM I 5.4.1 5.4.2 5.4.3 5.5 10-BIT A/D Converter (AD10 5.5.1 5.5.2 5.5.3 5.5.4 5.5.5 5.5.6 5.5.7 5.6 Controller Area Network (CAN 5.6.1 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 VDD Short Circuit Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 VCC Short Circuit Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Register Description ...
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... Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 4/126 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 CAN Transceiver Disabling function . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Interrupt generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 L9803 ...
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... L9803 List of tables Table 1. Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 2. Recommended Values for 16 MHz Crystal Resonator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 3. Watchdog Timing (fOSC = 16 MHz Table 4. Interrupt Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 5. I/O Port Mode Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 6. I/O Port Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 7. Port A Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 8. Port B Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Table 9. Clock Control Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Table 10. 16-Bit Timer Register Map and Reset Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Table 11 ...
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... List of figures List of figures Figure 1. L9803 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 2. Pin out Figure 3. Organization of Internal CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 4. Stack Manipulation on Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 5. External Clock Source Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 6. Crystal/Ceramic Resonator Figure 7. Clock Prescaler Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 8. Timing Diagram for Internal CPU Clock Frequency transitions . . . . . . . . . . . . . . . . . . . . . 20 Figure 9 ...
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... L9803 Figure 49. EEPROM Programming Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Figure 50. HiQUAD-64: qJA 116 Figure 51. HiQUAD-64: Thermal impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Figure 52. Application diagram example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Figure 53. HiQUAD-64 Mechanical Data & Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 List of figures 7/126 ...
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... General description 1.1 Introduction The L9803 is a Super Smart Power device suited to drive resistive and inductive loads under software control. It includes a ST7 microcontroller and some pheripherals. The microcontroller can execute the software contained in the program ROM and drive, through dedicated registers, the power bridge. ...
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... L9803 Figure 1. L9803 Block Diagram OSCIN OSCOUT NRESET TM CAN_H CAN_L Internal CLOCK OSC OSC SAFEGUARD CONTROL 8-BIT CORE ALU ROM 16K RAM 256B EEPROM 128B WATCHDOG CAN CONTROLLER RX TX CAN TRANSCEIVER General description VB1 PREREGULATOR VB2 POWER CC SUPPLY GND AGND ...
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... PA4/EXTCLK_1: PA4 I/O or External Clock on Timer 1. Before using this I/O as alternate input, it must be configured by software in input mode (DDR=0). In this case, this pin is a triggered floating input. Otherwise (I/O function), this pin is a triggered floating input or a push-pull output. 10/126 L9803 NU 51 PB1/EXTCLK_2 ...
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... L9803 PA5/OCMP2_2-PA6/OCMP1_2: I/Os or Output Compares on Timer 2. Alternate function software selectable (by setting OC2E or OC1E in CR2 register: bit 0041h). When used as alternate functions, these pins are push-pull outputs as requested by Timer 2. Otherwise, these pins are triggered floating inputs or push-pull outputs. PA7/ICAP2_2-PB0/ICAP1_2: I/Os or Input Captures on Timer 2. Before using these I/Os as alternate inputs, they must be configured by software in input mode (DDR=0) ...
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... PWM2 Control Register PWM2 Counter Register High PWM2 Counter Register Low RESERVED Miscellaneous Register Bridge Control Status Register Dedicated Control Status Register RESERVED Watchdog Control Register Watchdog Status Register EEPROM Control register RESERVED RESERVED L9803 Reset Remarks Status 00h R/W 00h R/W 00h R/W Absent 00h R/W ...
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... L9803 Table 1. Memory Map (continued) Register Address Block T1CR2 .. 0031h T1CR1 .. 0032h T1SR .. 0033h T1IC1HR .. 0034h-0035h T1IC1LR .. T1OC1HR .. 0036h-0037h T1OC1LR .. TIM1 T1CHR .. 0038h-0039h T1CLR .. T1ACHR .. 003Ah-003Bh T1ACLR .. T1IC2HR .. 003Ch-003Dh T1IC2LR .. T1OC2HR .. 003Eh-003Fh T1OC2LR .. 0040h T2CR2 .. 0041h T2CR1 .. 0042h T2SR .. 0043h T2IC1HR .. ...
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... FFE0h to (16384 bytes) FFFFh 14/126 User variables and subroutine nesting RESERVED including 4 bytes reserved for temperature sensor trimming (see 0C7CH: T0H 0C7DH: T0L 0C7EH: VT0H 0C7FH: VT0L RESERVED User application code and data Interrupt and Reset Vectors Description Section L9803 5.5.6) ...
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... L9803 2 Central Processing Unit 2.1 Introduction The CPU has a full 8-bit architecture. Six internal registers allow efficient 8-bit data manipulation. The CPU is capable of executing 63 basic instructions and features 17 main addressing modes. 2.2 CPU registers The 6 CPU registers are shown in the programming model in interrupt, all registers except Y are pushed onto the stack in the order shown in They are popped from stack in the reverse order ...
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... Carry/Borrow (C) When set, C indicates that a carry or borrow out of the ALU occured during the last arithmetic operation. This bit is also affected during execution of bit test, branch, shift, rotate and store instructions. 16/126 Figure 3 Figure 4), the PCL is stored at the first location pointed to by the L9803 in order to address the stack as it ...
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... L9803 Figure 4. Stack Manipulation on Interrupt CONTEXT RESTORED ON RETURN CONDITION CODE ACCUMULATOR X INDEX REGISTER PCH PCL Central Processing Unit CONTEXT SAVED ON INTERRUPT 0 LOWER ADDRESS HIGHER ADDRESS 17/126 ...
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... Table 2 40 Ω 56pF 56pF 1-10 MΩ : Maximum total capacitances on pins OSCIN and OSCOUT (the value OSC in EXTERNAL CLOCK . The circuit shown in Figure 6 lists the recommended capacitance and 60 Ω 150 Ω 47pF 22pF 47pF 22pF 1-10 MΩ 1-10 MΩ OSC out NC L9803 ; CPU is Ω . ...
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... L9803 Figure 6. Crystal/Ceramic Resonator Figure 7. Clock Prescaler Block Diagram C OSCin 3.1.2 External Clock An external clock may be applied to the OSCIN input with the OSCOUT pin not connected, as shown on Figure input. The equivalent specification of the external clock source should be used instead OXOV Clocks, Reset, Interrupts & Power saving modes ...
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... OSC/2 OSC/4 OSC/8 CPU CLK MISCELLANEOUS REGISTER b0 3.2 Oscillator safeguard The L9803 contains an oscillator safe guard function. This function provides a real time check of the crystal oscillator generating a reset condition when the clock frequency has anomalous value < reset is generated. OSC low If f > ...
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... L9803 This flag is useful for distinguishing Safeguard Reset, Power On / Low Voltage Reset and Watchdog Reset SGFL: Safeguard low flag. Set by an Oscillator Safeguard Reset generated for frequency too low, cleared by software (writing zero) or Power On / Low Voltage Reset. This flag is useful for distinguishing Safeguard Reset, Power On / Low Voltage Reset and Watchdog Reset SFGEN: Safeguard enable when set. It’ ...
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... Since no reset will be generated under these conditions, the Watchdog control register must be monitored by software. 22/126 = 16 MHz) OSC FFh C0h WATCHDOG STATUS REGISTER (WDGSR) RESET WATCHDOG CONTROL REGISTER (WDGCR) MSB 7-BIT DOWNCOUNTER CLOCK DIVIDER ÷ 12288 WDG timeout period (ms) 98.3 1.54 WDGF LSB L9803 ...
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... L9803 A flag in the watchdog status register indicates if the last reset is a watchdog reset or not, before clearing by a write of this register. 3.3.4 Register Description Watchdog Control Register (WDGCR) Register Address: 002Ah Reset Value: 0111 1111 (7Fh) 7 WDGA b7 = WDGA: Activation bit. This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the watchdog can generate a reset ...
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... SAFEGUARD (Internal source) The Reset Service Routine vector is located at address FFFEh-FFFFh. 24/126 - b4 Oscillator frequency / 4 Oscillator frequency / 8 Oscillator frequency / 16 Oscillator frequency / 32 Falling edge and low level (Reset state) Falling edge only Rising edge only Rising and Falling edge Option Option L9803 b0 ...
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... L9803 3.5.2 External Reset The NRESET pin is both an input and an open-drain output with integrated pull-up resistor. When one of the internal Reset sources is active, the Reset pin is driven low to reset the whole application. 3.5.3 Reset Operation The duration of the Reset condition, which is also reflected on the output pin, is fixed at 4096 internal CPU Clock cycles ...
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... Clocks, Reset, Interrupts & Power saving modes Figure 10. Power Up/Down behaviour Reset ON V Reset OFF V Reset UD POR/LVD 5V Figure 11. Reset Block Diagram V DD 300K NRESET 26/126 = undefined value Oscillator Signal to ST7 L9803 t t Internal RESET CLK RESET Reset Watchdog Reset Safeguard Reset POR/LVD Reset ...
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... L9803 3.6 Interrupts A list of interrupt sources is given in source. Interrupts are serviced according to their order of priority, starting with I0, which has the highest priority, and so to I12, which has the lowest priority. The following list describes the origins for each interrupt level: – I0 connected to Ports PA0-PA7, PB0-PB1 – ...
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... EEPROM Control INTERRUPT Y TRAP Y I BIT = 1 N SERVICE ROUTINE Interrupt source TOF_1 FFECh-FFEDh TOF_2 I8 FFEAh-FFEBh EOC I9 N/A I10 N/A I11 E2ITE I12 PUSH PC,X,A,CC ONTO STACK SET I BIT TO 1 LOAD PC WUTH APPROPRIATE (1) INTERRUPT VECTOR L9803 Vector Address FFF0h-FFF1h FFEEh-FFEFh FFE8h-FFE9h FFE6h-FFE7h FFE4h-FFE5h FFE2h-FFE3h ...
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... L9803 3.7 Power Saving Modes 3.7.1 Introduction There are three Power Saving modes. The Slow Mode may be selected by setting the relevant bits in the Miscellaneous register as detailed in may be entered using the WFI and HALT instructions. 3.7.2 Slow Mode In Slow mode, the oscillator frequency can be divided rather than by 2. The CPU and peripherals (except CAN, see Note) are clocked at this lower frequency ...
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... Figure 14. Halt Mode Flow Chart 30/126 HALT INSTRUCTION OSCILLATOR PERIPH. CLOCK CPU CLOCK I-BIT N N EXTERNAL INTERRUPT Y OSCILLATOR PERIPH. CLOCK CPU CLOCK I-BIT 4096 CPU CLOCK CYCLES DELAY FETCH RESET VECTOR OR SERVICE INTERRUPT OFF OFF OFF CLEARED RESET SET L9803 ...
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... L9803 4 Voltage Regulator 4.1 Introduction The on chip voltage regulator provides two regulated voltage, nominally 5V both. VCC supplies ADC and the analog periphery and VDD supplies the microcontroller and logic parts. These voltage are available at pins VDD and VCC to supply external components and connects a capacitors to optimize EMI performance ...
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... Warning: 32/126 ). When the output current exceeds this value the VDD voltage MAXVDD ). When the output current exceeds this value the VCC voltage MAXVCC The pin VB2 is not short circuit protected so a short circuit on this pin will destroy the device. L9803 ...
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... L9803 5 On-Chip Peripherals 5.1 I/O Ports 5.1.1 Introduction The internal I/O ports allow the transfer of data through digital inputs and outputs, the interrupt generation coming from an I/O and for specific pins, the input/output of alternate signals for the on-chip peripherals (TIMERS...). Each pin can be programmed independently as digital input (with or without interrupt generation) or digital output ...
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... In this case, the pin state is also digitally readable by addressing the DR register. Note: Input pull-up configuration can cause unexpected value at the input of the alternate peripheral input. When an on-chip peripheral use a pin as input and output, this pin has to be configured in input floating mode. 34/126 Figure 17). Push-Pull Vss V DD L9803 Open-drain Vss Floating ...
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... L9803 Figure 16. I/O Port General Block Diagram REGISTER ACCESS DR DDR OR OR SEL DDR SEL DR SEL EXTERNAL INTERRUPT SOURCE ( Table 5. I/O Port Mode Options Configuration Mode Floating with/without Interrupt Input Pull-up with/without Interrupt Push-pull Output Open Drain (logic level) True Open Drain Legend not implemented ...
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... Other transitions are potentially risky and should DR REGISTER ACCESS DR W REGISTER DATA BUS R ALTERNATE INPUT FROM OTHER PINS EXTERNAL INTERRUPT SOURCE (ei POLARITY SELECTION ANALOG INPUT DR REGISTER ACCESS R/W DR REGISTER ALTERNATE ALTERNATE ENABLE OUTPUT DR REGISTER ACCESS DR R/W REGISTER ALTERNATE ALTERNATE ENABLE OUTPUT L9803 ) x DATA BUS DATA BUS ...
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... L9803 be avoided, since they are likely to present unwanted side-effects such as spurious interrupt generation. Figure 17. Interrupt I/O Port State Transitions I/O Port Implementation The I/O port register configurations are resumed as following. Port PA(7:0), Port PB(2:0) DDR RESET status: DR=0, DDR=0 and OR=0 (Input mode, no interrupt). These ports offer interrupt capabilities. ...
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... Timer 1 (I0) wake-up interrupt Timer 1 (I0) wake-up interrupt Timer 1 (I0) wake-up interrupt Timer 1 (I0) wake-up interrupt #2 Timer 2 (I0) wake-up interrupt #1 Timer 2 (I0) wake-up interrupt Timer 2 (I0) Function Alternate Interrupt wake-up interrupt Timer 2 (I0) wake-up interrupt Timer 2 (I0) L9803 ...
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... L9803 Figure 18. Ports PA0-PA7, PB0-PB1I Alternate input Interrupt Alternate enable Alternate 1 M output Alternate latch enable Pull-up condition DDR latch OR latch OR SEL DDR SEL Alternate DR SEL 1 enable digital enable from other bits On-Chip Peripherals VDD P-BUFFER PAD ...
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... Reset Value: 0000 0000 (00h) 7 MSB Data direction registers (PADDR) Port A: 0001h Read/Write Reset Value: 0000 0000 (00h) (input mode) 7 MSB (PBDDR) Port B: 0005h Read/Write Reset Value: 0000 0000 (00h) (input mode) 7 MSB 40/126 L9803 0 LSB 0 LSB 0 LSB 0 LSB ...
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... L9803 Option registers (PAOR) Port A: 0002h Read/Write Reset Value: 0000 0000 (00h) (no interrupt) 7 MSB (PBOR) Port B: 0006h Read/Write Reset Value: 0000 0000 (00h) (no interrupt) 7 MSB 5.2 16-Bit Timer 5.2.1 Introduction The timer consists of a 16-bit free-running counter driven by a programmable prescaler. It may be used for a variety of purposes, including pulse length measurement two input signals (input capture) or generation two output waveforms (output compare and PWM) ...
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... Writing in the CLR register or ACLR register resets the free running counter to the FFFCh value. Both counters have a reset value of FFFCh (this is the only value which is reloaded in the 16-bit timer). The reset value of both counters is also FFFCh in One Pulse mode and PWM mode. 42/126 divided cpu Figure 19 on page 43. L9803 ...
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... L9803 The timer clock depends on the clock control bits of the CR2 register, as illustrated in Table 9: Clock Control or 524288 CPU clock cycles depending on the CC[1:0] bits. The timer frequency can be f Figure 19. Timer Block Diagram CPU CLOCK 8 high EXEDG 1/2 1/4 1/8 CC1 CC0 EXCLK ICF1 ICIE ...
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... CPU clock frequency. 44/126 Beginning of the sequence Read MSB At t0 LSB is buffered Other instructions Returns the buffered Read LSB At t0 +∆t LSB value at t0 Sequence completed L9803 ...
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... L9803 Figure 20. Counter Timing Diagram, internal clock divided by 2 INTERNAL RESET COUNTER REGISTER OVERFLOW FLAG TOF Figure 21. Counter Timing Diagram, internal clock divided by 4 INTERNAL RESET COUNTER REGISTER OVERFLOW FLAG TOF Figure 22. Counter Timing Diagram, internal clock divided by 8 INTERNAL RESET ...
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... This does not set any timer flags, and does not “wake-up” the MCU. If the MCU is awoken by an interrupt, the input capture flag will become active, and data corresponding to the first valid edge during HALT mode will be present. 46/126 f CPU/(CC1.CC0) Table 9: Clock Control Figure 23). L9803 ). Bits). ...
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... L9803 Figure 23. Input Capture Block Diagram ICAP1 EDGE DETECT CIRCUIT2 ICAP2 16-BIT 16-BIT Figure 24. Input Capture Timing Diagram TIMER CLOCK COUNTER REGISTER ICAPi PIN ICAPi FLAG ICAPi REGISTER ctive edge is rising edge. Note: A Output Compare In this section, the index, i, may because there are 2 output compare functions in the 16-bit timer ...
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... Clearing the output compare interrupt request (i.e.clearing the OCFi bit) is done by: 1. Reading the SR register while the OCFi bit is set access (read or write) to the OCiLR register. 48/126 MS Byte OCiHR f CPU/CC[1:0] Table 9: Clock Control ∆t f ⋅ CPU ∆OCiR = ---------------------- - PRESC Bits) ∆OCiR = ∆t · f EXT L9803 LS Byte OCiLR ). Bits). ...
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... L9803 The following procedure is recommended to prevent the OCFi bit from being set between the time it is read and the write to the OCiR register: – Write to the OCiHR register (further compares are inhibited). – Read the SR register (first step of the clearance of the OCFi bit, which may be already set). – ...
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... The OC1R register value required for a specific timing application can be calculated using the following formula: Where: 50/126 Table 9: Clock Control One pulse mode cycle OCMP1 = OLVL2 When event occurs Counter is reset on ICAP1 to FFFCh ICF1 bit is set When Counter OCMP1 = OLVL1 = OCR1 ⋅ CPU OCiR Value = --------------------- - 5 – PRESC L9803 Bits). ...
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... L9803 t = Pulse period (in seconds CPU clock frequency (in hertz) CPU PRESC = Timer prescaler factor ( depending on the CC[1:0] bits, seeTable 9: Clock Control If the timer clock is an external clock the formula is: Where Pulse period (in seconds External timer clock frequency (in hertz) EXT When the value of the counter is equal to the value of the contents of the OC1R register, the OLVL1 bit is output on the OCMP1 pin (See Figure 27) ...
Page 52
... If the timer clock is an external clock the formula is: Where: 52/126 Table 9: Clock Control Pulse Width Modulation cycle When Counter OCMP1 = OLVL1 = OCR1 OCMP1 = OLVL2 When Counter is reset Counter to FFFCh = OCR2 ICF1 bit is set ⋅ CPU OCiR Value = --------------------- - 5 – PRESC OCiR = t · EXT L9803 Bits). ...
Page 53
... L9803 t = Signal or pulse period (in seconds External timer clock frequency (in hertz) EXT The Output Compare 2 event causes the counter to be initialized to FFFCh (See on page 53). Note: 1 After a write instruction to the OCiHR register, the output compare function is inhibited until the OCiLR register is also written. ...
Page 54
... A falling edge triggers the capture rising edge triggers the capture. Bit 0 = OLVL1 Output Level 1. The OLVL1 bit is copied to the OCMP1 pin whenever a successful comparison occurs with the OCR1 register. CONTROL REGISTER 2 (CR2) Timer1 Register Address: 0031h Timer2 Register Address: 0041h 54/126 L9803 ...
Page 55
... L9803 Read/Write Reset Value: 0000 0000 (00h) 7 OC1E OC2E Bit 7 = OC1E Output Compare 1 Enable. 0: Output Compare 1 function is enabled, but the OCMP1 pin is a general I/O. 1: Output Compare 1 function is enabled, the OCMP1 pin is dedicated to the Output Compare 1 capability of the timer. Bit 6 = OC2E Output Compare 2 Enable. ...
Page 56
... The free running counter rolled over from FFFFh to 0000h. To clear this bit, first read the SR register, then read or write the low byte of the CR (CLR) register. Note: Reading or writing the ACLR register do not clear TOF. Bit 4 = ICF2 Input Capture Flag input capture (reset value) 56/126 TOF ICF2 OCF2 L9803 0 ...
Page 57
... L9803 1: An input capture has occurred.To clear this bit, first read the SR register, then read or write the low byte of the ICR2 (ICLR2) register. Bit 3 = OCF2 Output Compare Flag match (reset value) 1: The content of the free running counter has matched the content of the OCR2 register. ...
Page 58
... OUTPUT COMPARE 2 LOW REGISTER (OCLR2) Timer1 Register Address: 003Fh Timer2 Register Address: 004Fh Read/Write Reset Value: 0000 0000 (00h) This is an 8-bit register that contains the low part of the value to be compared to the CLR register MSB 58/126 L9803 0 LSB 0 LSB 0 LSB 0 LSB ...
Page 59
... L9803 COUNTER HIGH REGISTER (CHR) Timer1 Register Address: 0038h Timer2 Register Address: 0048h Read Only Reset Value: 1111 1111 (FFh) This is an 8-bit register that contains the high part of the counter value. 7 MSB COUNTER LOW REGISTER (CLR) Timer1 Register Address: 0039h ...
Page 60
... Timer2: 47 Reset Value 60/126 OCIE TOIE FOLV2 FOLV1 OC2E OPM PWM OCF1 TOF ICF2 OLVL2 IEDG1 OLVL1 CC1 CC0 IEDG2 EXEDG OCF2 - - L9803 0 LSB 0 LSB 0 LSB LSB - LSB - LSB - LSB - ...
Page 61
... L9803 Table 10. 16-Bit Timer Register Map and Reset Values (continued) Address Register 7 Name (Hex.) Timer1: 3E OCHR2 MSB - Timer2: 4E Reset Value Timer1: 3F OCLR2 MSB - Timer2: 4F Reset Value Timer1: 38 CHR MSB 1 Timer2: 48 Reset Value Timer1: 39 CLR MSB 1 Timer2: 49 Reset Value Timer1: 3A ACHR MSB ...
Page 62
... Whenever the 16 bits of the counter (defined as the PWM counter) overflow, the output level is set. The overflow value is defined by CYREG register. The state of the PWM counter is continuously compared to the PWM binary weight, as defined in DUTYREG register, and when a match occurs the output level is reset. 62/126 L9803 ...
Page 63
... L9803 Figure 29. PWM Cycle Note: If the CYREG value is minor or equal than DUTYREG value, PWM output remains set. With a DUTYREG value of 0000h, the PWM output is permanently at low level, no matter of the value of CYREG. With a DUTYREG value of FFFFh, the PWM output is permanently at high level. ...
Page 64
... Reset Value: 0000 0000 (00h) This is an 8-bit register that contains the high part of the value corresponding to the binary weight of the PWM pulse 7 MSB PWM CONTROL REGISTER (CONREG) PWM1 Register Address: 0014h PWM2 Register Address: 001Ch 64/126 L9803 0 LSB 0 LSB 0 LSB . 0 ...
Page 65
... L9803 Read/Write Reset Value: 0000 0000 (00h Bit 0= EN _PWM enables the PWM output disables PWM output. Bit 1= EN _INT enables interrupt request, 0 disables interrupt request. Bit PS2,PS1,PS0: prescaler bits The value of the PWM internal clock depends on these bits. ...
Page 66
... COMPARATOR1 COMPARATOR2 logic L9803 0 LSB =8MHz in PWM IRQ ...
Page 67
... Voltage thresholds are referred to the battery voltage connected to VBR pin. This pin must be used as reference for the K bus. Voltage drops between this pin and the battery line can cause thresholds mismatch between the L9803 ISO trasceiver and the counterpart trasceiver(s) connected to the same bus line. ...
Page 68
... PWMI Describe the register DCSR (0022h) as reported in Table 1. 68/126 I K 5µA 50KΩ Section Figure 34). PORT PA(7) ALTERNATE INPUT PA(7) PB(2) PWM PWM INPUT I/O DCSR 50KΩ 14V V K Figure 32). When the voltage 3.2.1), PWMI is directly connected with TIMER ICAP2 X 1 PIEN L9803 ...
Page 69
... L9803 5.5 10-BIT A/D Converter (AD10) 5.5.1 Introduction The Analog to Digital converter is a single 10-bit successive approximation converter with 4 input channels. Analog voltage from external sources are input to the converter through AD2,AD3 and AD4 pins. Channel 1 (AD1) is connected to the internal temperature sensor (see Section 5 ...
Page 70
... ADIE value is latched when ADST is set and this internal value holds all the conversion time long. 5.5.5 Temperature Sensing The AD1 input is internally connected to the output of a temperature sensing circuit. 70/126 inputs M logic U X latch start conversion end conversion WR DRH DRL L9803 2 Mhz Vin VCC sampling AGND + conversion ..... AD0 AD9 ...
Page 71
... L9803 The sensor generates a voltage proportional to the absolute temperature of the die. It works over the whole temperature range, with a minimum resolution of 1LSB/°K (5mV/°K) (Figure 36 shows the indicative voltage output of the sensor). Note The voltage output of the sensor is only related to the absolute temperature of the silicon junctions ...
Page 72
... When this bit is set a new conversion starts. ADST is automatically reset when the conversion is completed (COCO=1). Bits 1-0 = CH1-CH0 Channel Selection These bits select the analog input to convert. See 72/126 COCO ADIE 0 the trimming TRIM -80, max[T TRIM ADST CH1 Table 12 for reference. L9803 +80, TRIM 0 CH0 ...
Page 73
... L9803 Table 12. ADC Channel Selection Table CH1 DATA REGISTER HIGH (ADCDRH) Address: 0070h — Read Only Reset Value: 00000 0000 (00h Bit 1:0 = AD9-AD8 Analog Converted Value This register contains the high part of the converted analog value DATA REGISTER LOW (ADCDRL) Address: 0071h — ...
Page 74
... The same applies to overload frames which are recognized but never initiated. Figure 37. CAN Block Diagram TX/RX Buffer 1 10 Bytes RX BTL TX 74/126 ST7 Internal Bus ST7 Interface TX/RX TX/RX ID Buffer 2 Buffer 3 Filter 0 10 Bytes 10 Bytes 4 Bytes SHREG BCDL EML CRC CAN 2.0B passive Core L9803 PSR ID Filter 1 4 Bytes BRPR BTR ICR ISR CSR TECR RECR ...
Page 75
... L9803 5.6.2 Main Features ● Support of CAN specification 2.0A and 2.0B passive ● Three prioritized 10-byte Transmit/Receive message buffers ● Two programmable global 12-bit message acceptance filters ● Programmable baud rates MBit/s ● Buffer flip-flopping capability in transmission ● Maskable interrupts for transmit, receive (one per buffer), error and wake-up ● ...
Page 76
... BCDL: bit coding logic generating a NRZ-coded datastream with stuff bits. ● SHREG: 8-bit shift register for serialization of data to be transmitted and parallelisation of received data. ● CRC: 15-bit CRC calculator and checker. ● EML: error detection and management logic. ● CAN Core: CAN 2.0B passive protocol controller. 76/126 L9803 Figure 37): ...
Page 77
... L9803 Figure 38. CAN Frames Inter-Frame Space Inter-Frame Space Data Frame or Remote Frame Error Flag Any Frame Intermission End Of Frame or Error Delimiter or Overload Delimiter Overload Flag Modes of Operation The CAN Core unit assumes one of the seven states described below: ● STANDBY. Standby mode is entered either on a chip reset or on resetting the RUN bit in the Control/Status Register (CSR) ...
Page 78
... RESYNC FSYN & BOFF & 11 Recessive bits | (FSYN | BOFF) & 128 * 11 Recessive bits RUN IDLE Write to DATA7 | TX Error & NRTX Arbitration lost TRANSMISSION TX Error ERROR RUN & WKPS RUN & WKPS WAKE-UP Start Of Frame RECEPTION RX Error BOFF BOFF L9803 ...
Page 79
... L9803 monitored unless the node is not bus-off and the FSYN bit in the CSR register is set in which case a single sequence of 11 recessive bits needs to be monitored. ● IDLE. The CAN controller looks for one of the following events: the RUN bit is reset, a Start Of Frame appears on the CAN bus or the DATA7 register of the currently active page is written to. ● ...
Page 80
... When TECR or RECR > 127, the EPSV bit gets set ERROR ACTIVE When TECR and RECR < 128, the EPSV bit gets cleared BUS OFF L9803 ERROR PASSIVE When TECR > 255 the BOFF bit gets set and the EPSV bit gets cleared ). CAN ...
Page 81
... L9803 As a safeguard against programming errors, the configuration of the Bit Timing Register (BTR) is only possible while the device is in STANDBY mode. Figure 41. Bit Timing SYNC_SEG CAN 5.6.4 Register Description The CAN registers are organized as 6 general purpose registers plus 5 pages of 16 registers spanning the same address space and primarily used for message and filter storage ...
Page 82
... Cleared by software to set SCIF only on status changes and wake-up but not on all receive errors. Bit 5 = RXIE Receive Interrupt Enable − Read/Set/Clear Set by software to enable an interrupt request whenever a message has been received free of errors. Cleared by software to disable receive interrupt requests. 82/126 RXIE TXIE SCIE L9803 0 ORIE TEIE ETX ...
Page 83
... L9803 Bit 4 = TXIE Transmit Interrupt Enable − Read/Set/Clear Set by software to enable an interrupt request whenever a message has been successfully transmitted. Cleared by software to disable transmit interrupt requests. Bit 3 = SCIE Status Change Interrupt Enable − Read/Set/Clear Set by software to enable an interrupt request whenever the node’s status changes in run mode or whenever a dominant pulse is received in standby mode ...
Page 84
... The resulting baud rate can be computed by the formula: Note: Writing to this register is allowed only in Standby mode to prevent any accidental CAN protocol violation through programming errors. 84/126 BRP5 BRP4 BRP3 ------------------------------------------------------------------------------------------------- - × × BRP 1 BS1 + CPU L9803 0 BRP2 BRP1 BRP0 ) BS2 ...
Page 85
... L9803 BIT TIMING REGISTER (BTR) Read/Write in Standby mode Reset Value: 23h 7 0 BS22 BS2[2:0] determine the length of Bit Segment (BS2 + 1) BS2 CAN BS1[3:0] determine the length of Bit Segment (BS1 + 1) BS1 CAN Note: Writing to this register is allowed only in Standby mode to prevent any accidental CAN protocol violation through programming errors ...
Page 86
... When the counter value exceeds 127, the CAN controller enters the error passive state. Pages 1,2,3 Registers IDENTIFIER HIGH REGISTERS (IDHRx) 86/126 LID0 LRTR LDLC3 TEC5 TEC4 TEC3 REC5 REC4 REC3 L9803 0 LDLC2 LDLC1 LDLC0 0 TEC2 TEC1 TEC0 0 REC2 REC1 REC0 ...
Page 87
... L9803 Read/Write Reset Value: Undefined 7 ID10 ID9 ID[10:3] are the most significant 8 bits of the 11-bit message identifier.The identifier acts as the message’s name, used for bus access arbitration and acceptance filtering. IDENTIFIER LOW REGISTERS (IDLRx) Read/Write Reset Value: Undefined 7 ID2 ID1 ID[2:0] are the least significant 3 bits of the 11-bit message identifier. ...
Page 88
... RTR bit of the incoming message. If there is a match for the set of bits specified by the acceptance mask then the message is stored in a receive buffer. FILTER LOW REGISTERS (FLRx) Read/Write Reset Value: Undefined 7 FIL3 FIL2 88/126 FIL9 FIL8 FIL7 FIL1 FIL0 0 L9803 0 FIL6 FIL5 FlL4 ...
Page 89
... L9803 FIL[3:0] are the least significant 4 bits of a 12-bit message filter. MASK HIGH REGISTERS (MHRx) Read/Write Reset Value: Undefined 7 MSK11 MSK10 MSK[11:4] are the most significant 8 bits of a 12-bit message mask. The acceptance mask defines which bits of the acceptance filter should match the identifier and the RTR bit of the incoming message ...
Page 90
... Paged Reg12 Paged Reg11 Paged Reg12 Paged Reg13 Paged Reg12 Paged Reg13 Paged Reg12 Paged Reg13 Paged Reg14 Paged Reg13 Paged Reg14 Paged Reg13 Paged Reg14 Paged Reg15 6Fh Paged Reg14 Paged Reg15 Paged Reg14 Paged Reg15 Paged Reg15 Paged Reg15 L9803 ...
Page 91
... L9803 Figure 43. Page Maps PAGE 0 60h LIDHR 61h LIDLR 62h 63h 64h 65h 66h 67h Reserved 68h 69h 6Ah 6Bh 6Ch 6Dh TSTR 6Eh TECR 6Fh RECR Diagnosis Table 13. CAN Register Map and Reset Values Address Register Page (Hex.) Label CANISR ...
Page 92
... Short Circuit protection from transients in automotive environment ■ Slope control to reduce RFI and EMI ■ High speed (up to 1Mbaud) ■ If un-powered, L9803 CAN node does not disturb the bus lines (the transceiver is in recessive state). RECEIVER: ■ Differential input with high interference suppression ■ ...
Page 93
... Current consumption reduction, when disabling the trasceiver, can be as high as 15mA. Note When the CAN capabilities of L9803 are not needed additional consumption reduction can be achieved putting the CAN controller in Stand-by Mode. Figure 44. Can Bus Transceiver Block Diagram Š ...
Page 94
... PWM1/PWM2 Mode: PWM1 drives one side while PWM2 drives the other (two independent half bridges). 5.8.3 Functional Description A schematic description of the Power Bridge circuit is depicted in schematic the transistors must be considered in ON condition when they gate is high (set). 94/126 L9803 Figure 45. In this ...
Page 95
... L9803 Figure 45. Power Bridge Schematic SC_UL OVT UL DL OVT SC_DL EN bit in BCSR is the main enable signal, active high all the bridge transistors are switched off (UL, UR, DL and DR are reset) and the outputs OUTL and OUTR are in high impedance state. Being '0' the status after reset of EN, the bridge is in safe condition (OUTL=OUTR=Z). ...
Page 96
... Left or Right) to indicate the driving signal of the four DMOS. Conventionally a transistor is in the on status when its driving signal is set (‘1’) while off status when the driving signal is reset (‘0’). 96/126 (Table 14). (Table 14) uses symbols UL,R (Up Left or Right) and DR,L L9803 ...
Page 97
... L9803 Table 14. Functional Description Table Drive EN PWM_EN DIR PWM1 IN1 IN2 ...
Page 98
... Operation Configuration 1 BRAKE Full Bridge 1 FORWARD Full Bridge 1 BRAKE Full Bridge 0 BACK Full Bridge 0 BACK Full Bridge 1 FORWARD Full Bridge 1 FORWARD Full Bridge 0 BACK Full Bridge PWM1 ->left Two Half Bridges PWM2->right PWM1 ->left Two Half Bridges PWM2->right L9803 ...
Page 99
... L9803 Figure 46. Example - Power Bridge Waveform, PWM Up Brake Driving Mode 5.8.6 Register Description The power section is controlled by the microcontroller through the following register: POWER BRIDGE CONTROL STATUS REGISTER (PBCSR) Address: 0021h - Read/Write Reset Value: 00000000 7 PIE OVT Bit 0 = EN: Power Bridge enable. When reset the bridge is disabled and OUTL and OUTR are in high impedance condition ...
Page 100
... The erase and programming cycles are chained automatically. The global programming cycle duration is controlled by an internal circuit. 100/126 IN1 IN2 X X Direct 0 0 PWM1 Up Braking 0 1 PWM1 Down Braking 1 0 PWM1 Symmetrical 1 1 PWM1/PWM2 L9803 Driving Mode ...
Page 101
... L9803 Figure 47. EEPROM Block Diagram INTERRUPT REQUEST EEPCR ADDRESS BUS 5.9.2 Functional description Read operation (E2LAT=0) The EEPROM can be read as a normal ROM/RAM location when the E2LAT bit of the CR register is cleared. The address decoder selects the desired byte. The 8 sense amplifiers evaluate the stored byte which is put on the data bus. ...
Page 102
... Write bytes in the same row (with the same 12 Most Significant Bits of the ad- READ OPERATION POSSIBLE WRITE CYCLE EEPROM INTERRUPT E2LAT=0 E2PGM=0 (Read mode) E2LAT=1 E2PGM=0 Write bytes in EEPROM E2LAT=1 E2PGM=1 (Start programming cycle) Wait for end of programming (E2LAT=0 or interrupt) L9803 E2LAT E2PGM ...
Page 103
... L9803 5.9.3 Register Description EEPROM CONTROL REGISTER (EECR) Address: 002Ch - Read/Write Reset Value: 0000 0000 (00h Bit 7:3 = Reserved, forced by hardware to 0. Bit 2 = E2ITE: Interrupt enable. This bit is set and cleared by software. 0: Interrupt disabled 1: Interrupt enabled When the programming cycle is finished (E2PGM toggle from 1 to 0), an interrupt is generated only if E2ITE is high ...
Page 104
... If a write access happens while E2LAT=0, then the data on the bus will not be latched. The data latches are cleared when the user sets E2LAT bit. Note: Care should be taken in the write routine: the software has to read back the data and rewrite in case of failure. 104/126 L9803 ...
Page 105
... L9803 6 Instruction Set 6.1 ST7 Addressing Modes The ST7 Core features 17 different addressing modes which can be classified in 7 main groups: Addressing Mode Inherent Immediate Direct Indexed Indirect Relative Bit operation The ST7 Instruction set is designed to minimize the number of bytes required per instruction so, most of the addressing modes may be subdivided in two sub-modes called long and short: ● ...
Page 106
... Set Carry Flag Reset Carry Flag Reset Stack Pointer Load Clear Push/Pop to/from the stack Increment/Decrement Test Negative or Zero Complement Byte Multiplication Shift and Rotate Operations Swap Nibbles Pointer Pointer Size Length Address (Hex.) (Bytes 00..FF byte + 00..FF byte + 00..FF byte + 3 Function L9803 ...
Page 107
... L9803 Immediate: Immediate instructions have two bytes, the first byte contains the opcode, the second byte contains the operand value. . Immediate Instruction LD CP BCP AND, OR, XOR ADC, ADD, SUB, SBC Direct (Short, Long): In Direct instructions, the operands are referenced by their memory address, which follows the opcode ...
Page 108
... The offset is a word, thus allowing 64Kb addressing space and requires 2 bytes after the opcode. 108/126 Function Load Compare Logical Operations Arithmetic Additions/Substructions operations Bit Compare Function Clear Increment/Decrement Test Negative or Zero 1 or 2’s Complement Bit Operations Bit Test and Jump Operations Shift and Rotate Operations Swap Nibbles Call or Jump subroutine L9803 ...
Page 109
... L9803 Indirect (Short, Long): The required data byte to do the operation is found by its memory address, located in memory (pointer). Available Long and Short Indirect Instructions LD CP AND, OR, XOR ADC, ADD, SUB, SBC BCP Short Indirect Instructions Only CLR INC, DEC TNZ CPL, NEG ...
Page 110
... Arithmetic Additions/Substructions operations Bit Compare Function CLR INC, DEC TNZ CPL, NEG SWAP CALL, JP Function Conditional Jump Call Relative Clear Increment/Decrement Test Negative or Zero Complement Bit Operations Bit Test and Jump Operations Shift and Rotate Operations Swap Nibbles Call or Jump subroutine L9803 ...
Page 111
... L9803 The relative addressing mode consists of two sub-modes: Relative (direct): The offset is following the opcode. Relative (indirect): The offset is defined in memory, which address follows the opcode. 6.2 Instruction groups The ST7 family devices use an Instruction Set consisting of 63 instructions. The instructions may be subdivided into 13 main groups as illustrated in the following table: ...
Page 112
... A = FFH-A reg, M dec Y reg, M Pop CC inc X reg [TBL.w] jrf * Src L9803 ...
Page 113
... L9803 Mnemo Description JREQ Jump (equal) JRNE Jump (not equal) JRC Jump JRNC Jump JRULT Jump JRUGE Jump JRUGT Jump JRULE Jump Load MUL Multiply NEG Negate (2's compl) NOP No Operation OR OR operation ...
Page 114
... Pin Voltage, PWMI, PWMO pins Pin Voltage, CAN_H, CAN_L pins Input Current (low voltage pins) ≤ 0.3V Value -55 to +150 150 2000 GND - 0 0.3 DD GND - GND - -25.....+25 L9803 . Unit °C ° ...
Page 115
... L9803 7.2 Power considerations The average chip-junction temperature, T following equation: Where: is the Ambient Temperature in °C, – θ is the Package Junction-to-Ambient Thermal Resistance, in °C/W, – JA – the sum – the product of I INT expressed in Watts. This is the Chip Internal Power – ...
Page 116
... JA 2s1p 1Oz PCB Multilayer optimised PCB Dissipated power (W) 2s1p 1Oz PCB Multilayer optimised PCB Time (s) L9803 Die size 6x6 mm² T amb. 22 ºC Natural convection Die size 6x6 mm² Power amb. 22 ºC Natural convection 100 1,000 ...
Page 117
... L9803 7.3 Application diagram example Figure 52. Application diagram example VB GND VDD VCC GND GND CANH CANL PWMO PWMI * suggested ** needed *** needed for ADC input filtering and the values are depending on application VB 1N4002 VB1 SMCJ40A-TR VDD VCC GND VB2 VDD VCC AGND AGND ...
Page 118
... Halt mode (3) Low voltage pins -5 VB1 = 12V 8 VB1 = 12V 4.75 VB1 - VB1 = 3.. 6.4V 1.1 VB1 = 6.4..18V I =0..50mA VDD 4.75 VB1 - VB1 = 3.. 6.4V 1.1 VB1 = 6.4..18V I =0..15mA VCC 150 50 - 0.7xV L9803 Typ. Max Unit 5. ...
Page 119
... L9803 Table 18. DC Electrical Characteristics Symbol Parameter V Output Low Level Voltage OL V Output High Level Voltage OH I Input Leakage Current L I Pull-up Equivalent Resistance RPU T Output H-L Fall Time ohl T Output L-H Rise Time olh 1. All voltage are referred to GND unless otherwise specified. ...
Page 120
... TRIM +80, 150°C]. Precision is related to the read temperature in Kelvin. Parameter Conditions Measured on OUTL and OUTR. Measured on OUTL and OUTR. Short to VBL,VBR, GND: load short L9803 Min. Typ Max Unit 10 bit -2 2 LSB -1 ...
Page 121
... L9803 Table 21. POWER Bridge (continued) Symbol trp OUTL, OUTR rise time tfp OUTL, OUTR fall time Table 22. EEPROM Write time Write Erase Cycles Data Retention Table 23. PWM OUTPUT Symbol Parameter V Output Voltage High OH V Saturation Voltage Low SL I Input Current IO I Short circuit current PSC Table 24 ...
Page 122
... CANL High Level = DIFF - V CANL to RX DIFF = CANH CANL non return to zero Min. Typ 2.0 2 CANL -500 CANL 2.75 3.5 0.5 1.5 1.5 2 6.5V 900 = 6.1V 150 L9803 Max Unit 3 4.5 V 2.25 V 3.0 V 200 mA 200 150 V/µs 80 V/µs 200 ns 1 Mb/s ...
Page 123
... L9803 Table 27. Power on/low voltage reset Symbol V Input low level voltage Reset L V Input high level voltage Reset H I Input current Reset VDD for RESET undefined Reset UD V VDD low level for RESET on Reset ON V VDD high level for RESET off ...
Page 124
... ⊕ slug (bottom side (slug lenght OUTLINE AND MECHANICAL DATA HiQUAD- BOTTOM VIEW Gauge Plane C 0. SEATING PLANE COPLANARITY A1 POQU64ME L9803 ...
Page 125
... L9803 9 Revision history Table 28. Document revision history Date 09-Jun-2006 Revision 1 Initial release. Revision history Changes 125/126 ...
Page 126
... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 126/126 Please Read Carefully: © 2006 STMicroelectronics - All rights reserved STMicroelectronics group of companies www.st.com L9803 ...