L9803 STMicroelectronics, L9803 Datasheet - Page 88
L9803
Manufacturer Part Number
L9803
Description
Super Smart Power Motor Driver With 8-bit Mcu, Ram, Eeprom, Adc, Wdg, Timers, Pwm And H-bridge Driver
Manufacturer
STMicroelectronics
Datasheet
1.L9803.pdf
(126 pages)
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On-Chip Peripherals
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ACC = 0: Match for Filter/Mask0. Possible match for Filter/Mask1.
ACC = 1: No match for Filter/Mask0 and match for Filter/Mask1.
Reset by hardware when either RDY or RXIF gets reset.
Bit 2 = RDY Message Ready
−
Set by hardware to signal that a new error-free message is available (LOCK = 0) or that a
transmission request is pending (LOCK = 1).
Cleared by software when LOCK = 0 to release the buffer and to clear the corresponding
RXIF bit in the Interrupt Status Register.
Cleared by hardware when LOCK = 1 to indicate that the transmission request has been
serviced or cancelled.
Bit 1 = BUSY Busy Buffer
−
Set by hardware when the buffer is being filled (LOCK = 0) or emptied (LOCK = 1).
Reset by hardware when the buffer is not accessed by the CAN core for transmission nor
reception purposes.
Bit 0 = LOCK Lock Buffer
−
Set by software to lock a buffer. No more message can be received into the buffer thus
preserving its content and making it available for transmission.
Cleared by software to make the buffer available for reception. Cancels any pending
transmission request.
Cleared by hardware once a message has been successfully transmitted provided the early
transmit interrupt mode is on. Left untouched otherwise.
Note that in order to prevent any message corruption or loss of context, LOCK cannot be set
nor reset while BUSY is set. Trying to do so will result in LOCK not changing state.
Pages 4 Registers
FILTER HIGH REGISTERS (FHRx)
Read/Write
Reset Value: Undefined
FIL[11:4] are the most significant 8 bits of a 12-bit message filter. The acceptance filter is
compared bit by bit with the identifier and the RTR bit of the incoming message. If there is a
match for the set of bits specified by the acceptance mask then the message is stored in a
receive buffer.
FILTER LOW REGISTERS (FLRx)
Read/Write
Reset Value: Undefined
Read/Clear
Read Only
Read/Set/Clear
FIL11
FIL3
7
7
FIL10
FIL2
FIL9
FIL1
FIL8
FIL0
FIL7
0
FIL6
0
FIL5
0
FlL4
L9803
0
0
0
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