L9803 STMicroelectronics, L9803 Datasheet - Page 81

• Manufacturer Part Number: L9803
• Description: Super Smart Power Motor Driver With 8-bit Mcu, Ram, Eeprom, Adc, Wdg, Timers, Pwm And H-bridge Driver
• Manufacturer: STMicroelectronics

L9803
5.6.4
As a safeguard against programming errors, the configuration of the Bit Timing Register
(BTR) is only possible while the device is in STANDBY mode.
Figure 41. Bit Timing
Register Description
The CAN registers are organized as 6 general purpose registers plus 5 pages of 16
registers spanning the same address space and primarily used for message and filter
storage. The page actually selected is defined by the content of the Page Selection
Register. Refer to
General Purpose Registers
INTERRUPT STATUS REGISTER (ISR)
Read/Write
Reset Value: 00h
Bit 7 = RXIF3 Receive Interrupt Flag for Buffer 3
−
Set by hardware to signal that a new error-free message is available in buffer 3.
Cleared by software to release buffer 3.
Also cleared by resetting bit RDY of BCSR3.
Bit 6 = RXIF2 Receive Interrupt Flag for Buffer 2
−
Set by hardware to signal that a new error-free message is available in buffer 2.
Cleared by software to release buffer 2.
Also cleared by resetting bit RDY of BCSR2.
Bit 5 = RXIF1 Receive Interrupt Flag for Buffer 1
−
Set by hardware to signal that a new error-free message is available in buffer 1.
Cleared by software to release buffer 1.
Also cleared by resetting bit RDY of BCSR1.
Bit 4 = TXIF Transmit Interrupt Flag
−
Set by hardware to signal that the highest priority message queued for transmission has
been successfully transmitted (ETX = 0) or that it has passed successfully the arbitration
Read/Clear
Read/Clear
Read/Clear
Read/Clear
SYNC_SEG
RXIF3
1 x t
7
CAN
RXIF2
Figure
BIT SEGMENT 1 (BS1)
42.
RXIF1
t
BS1
NOMINAL BIT TIME
TXIF
SAMPLE POINT
SCIF
BIT SEGMENT 2 (BS2)
ORIF
t
BS2
On-Chip Peripherals
TEIF
TRANSMIT POINT
EPND
0
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