L9803 STMicroelectronics, L9803 Datasheet - Page 80

• Manufacturer Part Number: L9803
• Description: Super Smart Power Motor Driver With 8-bit Mcu, Ram, Eeprom, Adc, Wdg, Timers, Pwm And H-bridge Driver
• Manufacturer: STMicroelectronics

On-Chip Peripherals
80/126
Figure 40. CAN Error State Diagram
Bit Timing Logic
The bit timing logic monitors the serial bus-line and performs sampling and adjustment of
the sample point by synchronizing on the start-bit edge and resynchronizing on following
edges.
Its operation may be explained simply when the nominal bit time is divided into three
segments as follows:
●
●
●
●
To guarantee the correct behaviour of the CAN controller, SYNC_SEG + BS1 + BS2 must
be greater than or equal to 5 time quanta.
For a detailed description of the CAN resynchronization mechanism and other bit timing
configuration constraints, please refer to the CAN Specification - Bosh - Version 2.
When 128 * 11 recessive bits occur:
- the BOFF bit gets cleared
- the TECR register gets cleared
- the RECR register gets cleared
determine the stability of the network. Moreover, as one of the node status bits (EPSV
or BOFF of the CSR register) changes, an interrupt is generated if the SCIE bit is set in
the ICR Register. Refer to
Synchronisation segment (SYNC_SEG): a bit change is expected to lie within this
time segment. It has a fixed length of one time quanta (1 x t
Bit segment 1 (BS1): defines the location of the sample point. It includes the
PROP_SEG and PHASE_SEG1 of the CAN standard. Its duration is programmable
between 1 and 16 time quanta but may be automatically lengthened to compensate for
positive phase drifts due to differences in the frequency of the various nodes of the
network.
Bit segment 2 (BS2): defines the location of the transmit point. It represents the
PHASE_SEG2 of the CAN standard. Its duration is programmable between 1 and 8
time quanta but may also be automatically shortened to compensate for negative
phase drifts.
Resynchronization Jump Width (RJW): defines an upper bound to the amount of
lengthening or shortening of the bit segments. It is programmable between 1 and 4 time
quanta.
ERROR ACTIVE
When TECR or RECR > 127, the EPSV bit gets set
Figure
the EPSV bit gets cleared
When TECR and RECR < 128,
40.
BUS OFF
ERROR PASSIVE
When TECR > 255 the BOFF bit gets set
and the EPSV bit gets cleared
CAN
).
L9803