L9803 STMicroelectronics, L9803 Datasheet - Page 23

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L9803

Manufacturer Part Number
L9803
Description
Super Smart Power Motor Driver With 8-bit Mcu, Ram, Eeprom, Adc, Wdg, Timers, Pwm And H-bridge Driver
Manufacturer
STMicroelectronics
Datasheet

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L9803
3.3.4
3.4
A flag in the watchdog status register indicates if the last reset is a watchdog reset or not,
before clearing by a write of this register.
Register Description
Watchdog Control Register
(WDGCR)
Register Address: 002Ah
Reset Value: 0111 1111 (7Fh)
b7 = WDGA: Activation bit.
This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the
watchdog can generate a reset.
0: Watchdog disabled
1: Watchdog enabled.
b6-0 =T6-T0: 7 bit timer (Msb to Lsb)
These bits contain the decremented value. A reset is produced when it rolls over from 40h to
3Fh (T6 become cleared).
Watchdog Status Register
(WDGSR)
Register Address: 002Bh
Reset Value
b7-1 = not used
b0 = WDGF: Watchdog flag. Set by a Watchdog Reset, cleared by software (writing zero) or
Power On / Low Voltage Reset. This flag is useful for distinguishing Power On / Low Voltage
Reset and Watchdog Reset.
(*): Except in the case of Watchdog Reset.
Miscellaneous Register
(MISCR)
The Miscellaneous register allows the user to select the Slow operating mode and to set the
clock division prescaler factor. Bits 3, 4 determine the signal conditions which will trigger an
interrupt request on I/O pins having interrupt capability.
Register Address: 0020h — Read/Write
WDGA
7
-
7
(*)
: 0000 0000 (00h)
-
T6
-
— Read/Write
— Read/Write
T5
-
Clocks, Reset, Interrupts & Power saving modes
T4
-
T3
-
T2
-
T1
WDGF
0
T0
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