FMS6246 Fairchild Semiconductor, FMS6246 Datasheet - Page 6

• Manufacturer Part Number: FMS6246
• Description: 6th Order SD/PS Video Filter Driver
• Manufacturer: Fairchild Semiconductor

FMS6246 Rev. 1A
The same method can be used for biased signals with the addi-
tion of a pull-up resistor to make sure the clamp never operates.
The internal pull-down resistance is 800kΩ ±20% so the exter-
nal resistance should be 7.5MΩ to set the DC level to 500mV. If
a pull-up resistance less than 7.5MΩ is desired, an external
pull-down can be added such that the DC input level is set to
500mV.
The same circuits can be used with AC-coupled outputs if
desired.
NOTE: The video tilt or line time distortion will be dominated by
the AC-coupling capacitor. The value may need to be increased
beyond 220uF in order to obtain satisfactory operation in some
applications.
External Video
source must
be AC-coupled.
Figure 9.
Figure 6.
External video
source must
be AC-coupled.
Figure 7. DC-coupled inputs, AC-coupled Outputs
DVD or
DVD or
Output
Output
DAC
STB
SoC
DAC
STB
SoC
Figure 8.
75
75
Biased SCART with AC-Coupled Outputs
Biased SCART with DC-coupled Outputs
0.1u
0V - 1.4V
0.1u
500mV +/-350mV
AC-coupled inputs and outputs
500mV +/-350mV
0.1u
0V - 1.4V
7.5M
Inactive
Clamp
LCVF
7.5M
Clamp
Active
LCVF
Clamp
Active
LCVF
LCVF
Input
Bias
75
75
75
220u
220u
220u
75
6
Power Dissipation
The FMS6246 output drive configuration must be considered
when calculating overall power dissipation. Care must be taken
not to exceed the maximum die junction temperature. The fol-
lowing example can be used to calculate the FMS6246’s power
dissipation and internal temperature rise.
where P
and P
where
V
I
V
I
V
R
Board layout can also affect thermal characteristics. Refer to the
Layout Considerations Section for more information.
Layout Considerations
General layout and supply bypassing play major roles in high
frequency performance and thermal characteristics. Fairchild
offers a demonstration board, FMS6246DEMO, to use as a
guide for layout and to aid in device testing and characterization.
The FMS6246DEMO is a 4-layer board with a full power and
ground plane. Following this layout configuration will provide the
optimum performance and thermal characteristics. For optimum
results, follow the steps below as a basis for high frequency lay-
out:
• Include 10µF and 0.1µF ceramic bypass capacitors
• Place the 10µF capacitor within 0.75 inches of the power pin
• Place the 0.1µF capacitor within 0.1 inches of the power pin
• For multi-layer boards, use a large ground plane to help dissi-
• For 2 layer boards, use a ground plane that extends beyond
• Minimize all trace lengths to reduce series inductances
T
CH
CC
O
in
s
L
j
pate heat
the device by at least 0.5”
= T
= 5V
= channel load resistance
= 2V
= RMS value of input signal
= (I
= 60mA
CHx
A
CC
+ P
d
in
= P
= V
+ 0.280V
/ 6) + (V
d
• Θ
CH1
s
• I
JA
CH
+ P
O
- (V
CH2
/R
L
O
)
+ P
2
/R
L
CHx
)
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