FMS7401 Fairchild Semiconductor, FMS7401 Datasheet
FMS7401
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FMS7401 Summary of contents
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... The FMS7401L is intended for applications using a supply voltage in the 2.7V to 3.6V range fabricated using CMOS technology and is fully static offering a significant power savings. The FMS7401L is available in both 8-pin and 14-pin PDIP, SOIC and TSSOP packages. Features • 8-bit Microcontroller Core • ...
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... G6/- Vcc + REF G3/AIN1 G2/AIN2 G1/AIN3/ ADSTROBE Autozero Amplifier _ SR_GND x16 G4/AIN0 + Unit Gain A NC/GND OUT Figure 1. FMS7401L Block and Connection Diagram Pin Configurations G4/AIN0 1 8 GND 2 7 G2/AIN2 3 6 G1/AIN3 4 5 FMS7401L 8-Pin PDIP/SOIC 2 Vcc GND A OUT Analog Mux ...
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... General purpose I/O port (bit 7 of the I/O configuration registers). OUT AIN4 analog input of the ADC. Uncommitted amplifier analog output. In the FMS7401L, pin 8 is internally connected to GND. Externally, pin 8 should be left unconnected or connected to GND. Active low external reset input. In the FMS7401L, VCC is internally connected to pin 13. Externally, pin 13 should either be left unconnected or connected to pin 13 ...
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... FMS7401L Pin Definitions ...
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... Program Memory Erase 13 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 13.1 FMS7401L (2.7V to 3.6V Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Physical Dimensions ...
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... FMS7401L List of Figures Figure 1. FMS7401L Block and Connection Diagram Figure 2. BOR and POR Circuit Relationship Diagram Figure 3. Internal Clock Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 4. External Clock Scheme Figure 5. Recommended Halt/Idle Flow Figure 6. ADC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 7. Current Generator Interface Figure 8. Programmable Comparator Block Diagram (VLOOP = 0) Figure 9 ...
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... MHz FMS7401L 7 ...
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... FMS7401L 1 Reset Circuit The reset circuit in the FMS7401L contains four input conditions that trigger a main system reset. When the main system reset is triggered, a sequence of events occur defaulting all memory mapped registers (including the initialization registers) and I/Os to their initial states (see Table 1) ...
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... section of the datasheet for details. FMS7401L ...
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... FMS7401L 2 Clock Circuit The FMS7401L may be clocked using its internal oscillator circuit or using an external digital clock signal. The desired clock source is selectable by the CMODE bit of the Initialization Register 1. and the desired clock source (also called the device reference clock or F defaulted from the factory to use the internal oscillator as their main system instruction clock source. After power-up, the inter- nal oscillator runs continuously unless entering Halt Mode or using an external clock source. Table 2. CMODE Bit Defi ...
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... FMS7401L output (see Table 3). The FS bits may the PLL’s F output OSC (FS=0) 4 selects between the F 5 Any attempts to write to Power Saving Modes ...
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... Refer to the Device Memory section of the datasheet for details regarding the Initialization Registers 1. 2. The upper F frequency (4MHz) is not a standard feature offered on the FMS7401L devices but is available upon request. OSC 3. The ADCNTRL2 register is defined in the ADC Circuit 4. The PSCALE register is defined in the PWM Timer 1 Circuit 5. Software must always configure the device’ ...
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... PRODUCT SPECIFICATION 3 Power Saving Modes The FMS7401L has both Halt and Idle power saving modes. Each mode is controlled by software and offers the advantage of reducing the total current consumption of the device in an application. For all current consumption details, please refer to the Electrical Characteristics section of the datasheet ...
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... FMS7401L enabled, it must complete the lock phase before software may enable the use of the outputs to clock any of the device circuits. Therefore, upon exiting Halt Mode software must wait the T frequency and in phase. 1. Initially, the PLLEN bit of the PSCALE register must be set in order to enable the PLL circuit. ...
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... The MIW and Timer 0 Circuits are described later in the datasheet. 2. Refer to the Electrical Characteristics section of the datasheet for details. 3. Refer to the Clock Circuit’s PLL section of the datasheet for details. 4. The FSEL bit in the PSCALE register must be set. REV. 1.0.3 1/24/05 wait time. . PLL_LOCK FMS7401L 15 ...
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... ADC Circuit The Analog-to-Digital Converter (ADC) Circuit extends the features of the FMS7401L by offering a 5-channel 8-bit ADC. The ADC may be programmed to convert voltages on any of the eight inputs of the analog mux, where five are multifunction input channels (ACH1-ACH5) and three are used for system calibration. The integrated ADC function offers a single cost-effective solution for applications requiring voltage, current and temperature sensing. The multifunction input channels may be confi ...
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... ADSTROBE ACH1 S/H Y ACH5 AGND +V REF Analog Voltage +V REF Generator Vcc/3 +V Vcc Voltage Level Generator VLOOP 6 COMPLEV 0.23R Sel ENAMP 4 SAR LOGIC 8 8 AREF F RCLK2 DELTIME 4 Programmable PWMOFF Delay +V REF REF AREF Y Vcc B Sel REFSEL ACH5 FMS7401L 17 ...
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... FMS7401L Bit 6 of the ADCNTRL1 register is the ADC’s microcontroller hardware interrupt enabled (AINTEN) bit. If set, hardware interrupts (ADCI) are enabled and triggered by the APND pending flag. interrupt will continue to execute software’s ADC interrupt service routine until the pending flag is cleared. ...
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... The REFBY2 bit config- RCLK1 section of the datasheet for addition details. and G7/A ) may be used as normal I/O ports. The G7/AIN4 pin may IN OUT clock for synchronization with the PWM Timer 1’s ADSTROBE output signal. The FMS7401L Bit 2 Bit 1 Bit 0 ACHSEL[3:0] for details. Analog Channel I/O Equiv. ...
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... FMS7401L options must be prepared prior to setting the ENDAS bit. Refer to the following additional details. The ADSTROBE signal is generated by the PWM Timer 1 circuit and is configured using its T1CMPB and T1RA registers. Refer to the PWM Timer 1 Circuit the ADC circuit is configured to accept only ADC start commands issued by software when setting the ASTART bit of the ADCNTRL1 register to 1 ...
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... ADCNTRL2 Register (addr. 0xA0) Bit 4 Bit 3 ENDAS ASPEED[1:0] is the inverting input and G7/A IN ADCLK /2 ADCLK /4 ADCLK /8 ADCLK . SRC section for details. FMS7401L Bit 2 Bit 1 Bit 0 ENIS GAIN Clock is the amplifier output. The OUT ADC Conversion Clock Configuration must be configured to ADCLK 21 ...
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... FMS7401L this information because the APND bit may be triggered before the ASTART is automatically cleared. The ADC conversion completion delay may occur when the F 4.2.1 Analog Input Voltage and its 8-bit Digital Result The relationship between the 8-bit digital value stored in the ADATA register and the analog input voltage is as follows: ...
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... I/O circuitry. The IN OUT ) is internally fed to the Programmable OUT . An ADC conversion may be triggered to con- REF 1 Figure 7 provides an example of a typical ISOURCE application where the FMS7401L 8 A greater divide factor may still port pins. Before enabling the AMP . REF of current typically SRC 23 ...
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... The ADC hardware interrupt will be executed in the defined priority order. Refer to the 7. Assuming the internal oscillator frequency is F OSC 8. The upper F frequency (4MHz) is not a standard feature offered on the FMS7401L devices but is available upon request. OSC 9. Refer to the I/O Ports section of the datasheet for details. ...
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... The inverting input of the comparator is controlled by the Voltage Loop 9). COMP Register (addr. 0xA0) Bit 4 Bit 3 CL[5:0] Table 9 Table 9 and Table 10). The comparator output (C signal will equal zero if the G4/AIN0 or G2/AIN2 input voltage OUT FMS7401L , VLOOP=1, the THL THU ) connected to OUT Bit 2 Bit 1 Bit 0 VLOOP COUT and Table 10 for details ...
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... FMS7401L Bits 7-2 (CL[5:0]) is the comparator voltage threshold level selection bits of the Comparator Control (COMP) register. The CL bits may be programmed to select one of the voltage threshold levels as the inverting input of the analog comparator. Refer to Table 9 and Table 10 for a detailed list of voltages. Bit 1 of the Comparator Control (COMP) register is the Programmable Comparator circuit’s voltage loop (VLOOP) configura- tion enable bit. If VLOOP=0, the Programmable Comparator circuit is confi ...
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... FMS7401L CL[0] Voltage Reference 1 35mV 0 50mV 1 64mV 0 78mV 1 93mV 0 107mV 1 121mV 0 135mV 1 150mV 0 164mV 1 178mV 0 192mV 1 205mV 0 219mV 1 233mV 0 247mV 1 261mV 0 274mV 1 ...
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... PWM duty cycle (see FMS7401L voltage/current loop configuration can be used in SMPS applications where the digital loop control does not have the required accuracy and speed. Refer to the tion details ...
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... OUT EPWM DD[3] DD[2] DD[1] DD[ RCLK2 Comparator + _ VLOOP 0.23R R V REF OUT ) signal. If the Programma- OUT ) clock into the COUT bit of ICLK DDELAY Register PWMOFF (WKEN[6]) DIGITAL DELAY CIRCUIT C COMP Register Programmable Reference ACH5 FMS7401L If OUT 29 ...
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... FMS7401L 5.3 Digital Delay Filter with PWMOFF Output The Programmable Comparator’s output (C signal toggles from when the external input (G4/AIN0 or G2/AIN2) voltage is higher than the programmed voltage threshold or Uncommitted Amplifier output (A the programmable digital delay counter to begin incrementing. With each digital delay count, its value is compared against the value stored in the DD[3:0] bits of the Digital Delay (DDELAY) control register ...
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... DDELAY Register (addr. 0xA2) Bit 4 Bit 3 OFFMODE device pin. IN triggers high • (1/F ) DDELAY RCLK2 Figure 10. Digital Delay Timing Comparator Output Digital Delay T DDELAY Start Sample PWMOFF T1HS1 T1HS2 clock. RCLK2 FMS7401L Bit 2 Bit 1 Bit 0 DD[3:0] device pin). IN after the programmed delay (T OUT DDELAY 8-Bit ). 31 ...
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... Software must access the six memory mapped PWM Timer 1 registers to configure and control the Timer 1 circuit. Prescale (PSCALE) register is used to configure the entire FMS7401L clock structure including the Timer 1’s F bit Timer 1 Compare A (T1CMPA), Timer 1 Compare B (T1CMPB), and Timer 1 Reload (T1RA) registers are used to define the PWM output signal’ ...
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... ICLK to obtain a wider frequency T1CLK Bit 1 Bit 0 Bit 2 PS[2:0] ) source. ICLK ) source. ICLK =2 MHz) OSC Max PWM Freq. (12-bit resolution) FSEL=0 FSEL=1 FMODE=0 FSEL=1 31.25 kHz 244.14 Hz 1.95 kHz 62.5 kHz 244.14 Hz 3.9 kHz 125 kHz 244.14 Hz 7.8 kHz 250 kHz 244.14 Hz 15.625 kHz FMS7401L 13). 33 ...
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... FMS7401L Table 14. Timer 1 Prescale Selection (PS) Bits PS[2] PS[ 6.1.2 PWM Cycle Configuration Registers The PWM Timer 1 circuit has three 12-bit (T1CMPA, T1CMPB, T1RA) and one 5-bit (DTIME) configuration registers used to specify the duty cycle and period of the Timer 1 output signals. Upon a system reset, all four registers are initialized with ones (0xFFF, 0x1F). All confi ...
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... Bit 4 Bit • DT completes, will dictate the circuit’s attribute for the next PWM cycle. When DT passes completing the current PWM cycle. The last T1BOUT value after the T FMS7401L Bit 2 Bit 1 Bit 0 DT[4:0] completes DT completes, will dictate the circuit’s DT passes completing the current ...
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... FMS7401L pletes, will dictate the device’s I/O attribute for the next PWM cycle. When reading the T1BOUT, the value reported will be the last value written by software and may not necessarily reflect the device’s I/O attribute for the current PWM cycle. Bit 4 (T1C0) of the T1CNTRL register has two functions depending on Timer 1’s selected operating mode. In PWM Mode, when T1C0=1, the TMR1 circuit becomes enabled and begins to increment from its initial 0x000 state ...
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... Bit 4 Bit 3 T1C0 T1PND Table 17 for details. Table 17 for details. Table 17 for details. Timer Mode Source PSCALE Register and Timer 1 Clock Configuration FMS7401L Bit 2 Bit 1 Bit 0 T1EN X T1BOUT Interrupt Timer count on TMR1 Overflow Prescaler Input TMR1 Overflow Prescaler Input TMR1 Overfl ...
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... FMS7401L The PWM Timer 1 can be programmed to toggle one or both PWM output signals (T1HS1 and T1HS2) to support a variety of output configurations (half bridge, full bridge, half-bridge driver and are enabled by programming the T1C1 and T1C2 bits in the T1CNTRL register (see T1HS1 (G0) and T1HS2 (G5) output signals may be configured with opposite phases and dead time controlled edges (see Figure 12). The phases of the output signals are confi ...
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... Dead Time Control 12 [11:0] T1PND T1RA 5 DT[4:0] DTIME PWM Sample Sample ADC ADC & Conversion Conversion Hold T CONV ENDAS ADSTROBE T1BOUT PWMOFF PORTGD Sample ADC ADC & & Conversion Conversion Hold Hold FMS7401L G1/AIN3 T1HS2/G5 T1HS1/G0 39 ...
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... FMS7401L 6.3 Input Capture Mode When the PWM Timer 1 circuit is configured in Input Capture Mode, the T1HS2 signal is used as an input of the Timer 1 circuit instead of an output as in PWM Mode. The G5/T1HS2 device pin should be configured by software as an input port. The Timer 1 circuit may be programmed to capture the TMR1 counter value in the T1RA register with every rising or falling edge transition of the T1HS2 input ...
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... A Watchdog Timer runs continuously with Timer 0’s main 12-bit up-counter; however, a Watchdog Reset will not REV. 1.0.3 1/24/05 1 The T0PND flag is automatically set with each counter overflow Multi-input Wakeup Circuit 3 4 T0CNTRL Register (addr. 0xB6) Bit 4 Bit FMS7401L ICLK section of the datasheet. The T0INTEN Bit 2 Bit 1 Bit 0 x T0PND T0INTEN ). The 41 ...
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... Refer to the Device Memory section of the datasheet for details regarding the Initialization Registers. 7. The FMS7401L must be placed in a special programming mode in order to have full write and read access of all of the device memories. Refer to the Programming Specification section of the datasheet for details. ...
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... Bit 5 Bit 4 Bit Port Pin Configuration PORTGD Bit 0 High-impedance input (tri-state input) 1 Input with pull-up (weak one input) 0 Push-pull zero output 1 Push-pull one output FMS7401L 14). The bi-directional I/O pins can be indi- GX Table 20 provides Bit 2 Bit 1 Bit ...
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... Therefore, the “LD WKPND, #0F7H” instruction will clear the WKPND[3] while all others bits remain the same. REV. 1.0.3 1/24/05 2 The WKEN, WKEDG and WKPND are 8-bit registers where each bit corresponds to sections of the datasheet for addition details. 2 The WKINTEN bit enables hardware interrupts for the MIW circuit if set FMS7401L 1 with an external event, 44 ...
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... FMS7401L The MIW circuit can be used with the I/O ports configured as both an input and output. The MIW configuration and function is the same for both I/O configurations. However, when using the MIW circuit to wake the device from Halt/Idle Mode the wakeup I/O port must be configured as an input, otherwise the device will never exit the mode. ...
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... PRODUCT SPECIFICATION 10 8-Bit Microcontroller Core The FMS7401L’s 8-bit microcontroller core is specifically designed for low cost applications involving bit manipulation, shift- ing and block encryption based on a modified Harvard architecture meaning peripheral, I/O and RAM locations are addressed separately from instruction data. ...
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... FMS7401L 10.1.1 Accumulator (A) The Accumulator is a general-purpose 8-bit register that is used to hold data and results of arithmetic calculations or data manipulations. 10.1.2 X-Pointer (X) The X-Pointer register allows for an 11-bit indexing value to be added to an 8-bit offset creating an effective address used for reading and writing among the memory space. This provides software with the flexibility of storing lookup tables in the code EEPROM memory space for the core’ ...
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... G can be set within an interrupt service routine, “nesting” interrupts in this way should only be done when there is a clear understanding of latency and of the arbitration mechanism. Table 23. Interrupt Priority Sequence Priority (5 highest, 1 lowest REV. 1.0.3 1/24/05 Interrupt Software (INTR) MIW (EDGEI) Timer 0 (TMRI0) PWM Timer 1 (TMRI1) ADC (ADCI) FMS7401L 48 ...
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... Interrupt Pending Flags T1EN REV. 1.0.3 1/24/05 Table 17). The execution of the INTR instruction generates a software interrupt. Once the Figure 17. Basic Interrupt Structure T0INT WKINT AINT Interrupt Enable Bits FMS7401L 30). This process takes five instruction Table 23 for the interrupt Interrupt G Global Interrupt Enable 49 ...
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... If bit 5 is zero, the address for the next instruction executed is determined by subtracting the lower 5 bits of the opcode (0xC1-0xDF) from the program counter; otherwise, the lower 5 bits of the opcode (0xE0-0xFF) are added to 6 the program counter. REV. 1.0.3 1/24/ 8-bit or 12-bit immediate field as an operand. Immediate 5 FMS7401L 50 ...
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... FMS7401L Table 24. Instruction Addressing Modes Instruction Immediate ADC A, # ADD A, # AND SUBC A, # XOR A, # CLR INC DEC IFEQ IFGT IFNE IFLT IFC IFNC INVC LDC STC RLC RRC NOP IFBIT #, A IFNBIT #, A SBIT RBIT JP JSR JMP RET ...
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... ST 2 None ST 1 None STC 1 None SUBC 3 None SUBC 1 None SUBC 2 None SUBC 2 None XOR 3 None XOR 3 None XOR 1 Z,N XOR 2 Z,N FMS7401L Flags Operand Bytes Cycles affected None None [#, None 1 1 None None [#, ...
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... The content of XHI (X[10:8]) is ignored. 5. The program memory space for the FMS7401L is 0xC00 to 0xFFF; however, the program counter will use only the 10 least significant bits of the address provided. 6. Although the JP instruction can jump forward 31 bytes, it can only jump backwards 30 bytes because the program counter is automatically incremented while the JP instruction is being executed ...
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... PRODUCT SPECIFICATION 11 Device Memory The FMS7401L has 64 bytes of SRAM and 64 bytes of EEPROM (data EEPROM) available for data storage. It also has 1K Byte of EEPROM (code EEPROM) memory for program storage. During the device’s normal operation, software has both read and write access of SRAM and data EEPROM memories but has only read access of the code EEPROM. ...
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... FMS7401L prior to leaving the factory with the appropriate calibration value and with the ports configured as tri-state inputs. In program- ming mode, the default port configuration may be changed; however, be sure to maintain the factory current source calibration value since writes to a single register must affect all bits. ...
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... T1HS1 input with pull-up, T1HS2 input tri-state 0 T1HS1 input tri-state, T1HS2 input with pull-up 1 T1HS1 and T1HS2 input with pull-up 0 T1HS1 and T1HS2 push-pull 0 outputs 1 T1HS1 push-pull 1 output, T1HS2 push-pull 0 output 0 T1HS1 push-pull 0 output, T1HS2 push-pull 1 output 1 T1HS1 and T1HS2 push-pull 1 outputs FMS7401L Description 56 ...
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... FMS7401L 11.2 Memory Map All I/O ports, peripheral registers, and core registers (except the accumulator and the program counter) are mapped into the memory space. Table 30. Memory Mapped Registers Address Memory Space 0x00 – 0x3F Data 0x40 – 0x7F Data 0x9D Data 0x9F ...
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... The FMS7401L’s normal mode operation begins after a system reset and is when the 8-bit microcontroller core begins executing the instruction program residing in the code EEPROM memory. 2. The FMS7401L must be placed in a special programming mode of operation in order to have full write and read access of all of the device memories. Refer to the In-circuit Programming Specification section of the datasheet for details ...
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... FMS7401L 12 In-circuit Programming Specification The FMS7401L supports in-circuit programming of all internal memory mapped registers including the data EEPROM, code EEPROM, and initialization registers. In-circuit programming consists of a 4-wire serial interface used to place the device in pro- gramming mode and issue all programming commands. ...
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... Byte Write Sequence After the external programmer puts the FMS7401L into programming mode, the LOAD pin must be set to Vcc before serially shifting the first 32-bit command word using the SHIFT_IN and CLOCK signals. By definition, bit 31 of the command word must be shifted fi ...
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... FMS7401L between the device and external programmer hardware. The device sets SHIFT_OUT low during a page-write command by the time the external programmer has issued the second rising edge of CLOCK informing the programmer that the memory write is in progress. The external programmer must wait T Vcc to initiate the next command cycle ...
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... DOH 32-bit Command = Page Write from address 0xC10 Page 1 0x90 0x00 0x10 Byte 1 PageWr (First) 32 Clock Cycles Page Write Ready FMS7401L ...
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... After the external programmer puts the FMS7401L into programming mode, the LOAD pin must be set to Vcc before serially shifting the first 32-bit program erase command word using the SHIFT_IN and CLOCK signals. By definition, bit 31 of the command word must be shifted fi ...
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... Vcc Input Voltage Lead Temperature (10s max) Electrostatic Discharge on all pins Internal Voltage Regulator output current Operating Conditions Relative Humidity (non-condensing) EEPROM write limits REV. 1.0.3 1/24/05 Min. Typ. Max. -65 +150 -0.3 Vcc + 0.3 4.0 +300 2000 5 95% See AC Electrical Characteristics FMS7401L Unit ° ° ...
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... FMS7401L 13.1 FMS7401L (2.7V to 3.6V) DC Electrical Characteristics All measurements are valid for T =+25°C unless otherwise stated. A Symbol Parameter 1 I Active Supply Current CC (without data EEPROM writes in progress) Active Supply Current (with data EEPROM writes in progress) Active Supply Current (without data EEPROM writes in progress) ...
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... Conditions Min. 2.64 -40°C to +85°C 2.60 -40°C to 125°C 2.59 Conditions Min. -6% -40°C to 125°C -8% V – 30mV THU -40°C to 125°C V – 35mV THU 2mV overdrive 5mV overdrive 10mV overdrive FMS7401L Min. Typ. Max. Units 1.96 2.00 2.04 MHz -0.5 +0 2.00 MHz 60 µS 3.7 ...
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... FMS7401L ADC Electrical Characteristics All measurements are valid for T =+25°C unless otherwise stated. A Parameter 3 ADC Integral Non Linearity (INL) Best Fit ADC Differential Non 3 Linearity (DNL) 3 ADC Conversion Time 3 Internal Voltage Reference (V ) REF 3 Amplifier x16 Gain Error Current Source (I ) SRC ...
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... Figure 23. Icc Active vs. Temperature (no PLL or data EEPROM writes) 900 850 800 750 700 650 600 -40 REV. 1.0.3 1/24/05 ) vs. Temperature OSC Internal Oscillator Frequency (F ) vs. Temperature OSC 0 25 Temperature (°C) Icc Active vs. Temperature (no PLL or data EEPROM writes Temperature (°C) FMS7401L 3.6V 3.3V 2.7V 85 125 3.6V 3.3V 2.7V 85 125 68 ...
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... FMS7401L Figure 24. Icc Active vs. Temperature (no PLL, with data EEPROM writes) 1100 1050 1000 950 900 850 800 750 700 -40 Figure 25. Icc Active vs. Temperature (with PLL, no data EEPROM writes) 8.5 8.0 7.5 7.0 6.5 6.0 5.5 5.0 4.5 -40 69 Icc Active vs. Temperature (no PLL, with data EEPROM writes Temperature (°C) Icc Active vs. Temperature ...
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... PRODUCT SPECIFICATION 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 -40 Figure 27. Idle Current vs. Temperature (no PLL) 210 200 190 180 170 160 150 -40 REV. 1.0.3 1/24/05 Figure 26. Halt Current vs. Temperature HALT Current vs. Temperature 0 25 Temperature (°C) Idle Current vs. Temperature (no PLL Temperature (°C) FMS7401L 3.6V 3.3V 2.7V 85 125 3.6V 3.3V 2.7V 85 125 70 ...
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... FMS7401L Figure 28. Idle Current vs. Temperature (with PLL) 1.70 1.60 1.50 1.40 1.30 1.20 -40 2.5 2.0 1.5 1.0 0.5 0 Idle Current vs. Temperature (with PLL Temperature (°C) Figure 29 25°C (G1–G4, G6 25° (G1-G4, G6, G7 (mA) OL PRODUCT SPECIFICATION 3.6V 3.3V 2.7V 85 125 3.6V 3.3V 2. REV. 1.0.3 1/24/05 ...
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... PRODUCT SPECIFICATION 2.5 2.0 1.5 1.0 0.5 0.0 2 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 2 REV. 1.0.3 1/24/05 Figure 30 25°C (G0 25° (G0, G5 (mA) OL Figure 31 25°C (G1–G4, G6, G7 ° vs (G1-G4, G6, G7 (mA) OH 3.6V 3.3V 2. 3.6V 3.3V 2. FMS7401L 72 ...
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... FMS7401L 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 2 2.75 2.74 2.74 2.73 2.73 2.72 2.72 2.71 2.71 2.70 -40 73 Figure 32 25°C (G0 25° (G0, G5 (mA) OH Figure 33. BOR Level vs. Temperature Brown-out Reset Level vs. Temperature Temperature (°C) PRODUCT SPECIFICATION 3.6V 3.3V 2.7V 15 BOR Level 125 REV. 1.0.3 1/24/05 ...
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... Figure 34. Programmable Comparator Voltage Level vs. Temperature 2.5 2.0 1.5 1.0 0.5 0.0 -40 1.222 1.22 1.218 1.216 1.214 1.212 1.21 1.208 1.206 1.204 1.202 -40 REV. 1.0.3 1/24/05 Programmable Comparator Voltage Level vs. Temperature 0 25 Temperature (°C) Figure 35. V vs. Temperature REF V vs. Temperature REF 0 25 Temperature (°C) FMS7401L Level 1 Level 31 Level 47 Level 63 85 125 3.6V 3.3V 2.7V 85 125 74 ...
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... FMS7401L Figure 36. Current Source (I 1040 1030 1020 1010 1000 990 980 970 960 950 940 -40 2.0 1.5 1.0 0.5 0.0 -0.5 -1.0 -1.5 -2.0 - vs. Temperature SRC Current Source (I ) vs. Temperature SCR Temperature (°C) Figure 37. Gain 16 Error vs. Temperature Gain 16 Error vs. Temperature Temperature ( ° C) PRODUCT SPECIFICATION 3.6V 3.3V 2.7V 125 3.6V 3.3V 2.7V 125 ...
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... Timer 1, Timer 0, ADC, Uncommitted Amplifier, and Programmable Comparator circuits all active. 2. Refer to the Clock Circuit section of the datasheet for details regarding the FMS7401L’s main system instruction clock (F 3. The parameter is guaranteed by design but is not 100% tested. 4. The I Idle current is based on a continuous Idle Mode looping program and is dependent on the program code. ...
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... FMS7401L Ordering Information FSID Package FMS7401LEN PDIP8 FMS7401LVN PDIP8 FMS7401LEN14 PDIP14 FMS7401LVN14 PDIP14 FMS7401LEM8X SOIC8 FMS7401LEMX SOIC14 FMS7401LEMT8X TSSOP8 FMS7401LEMTX TSSOP14 77 Supply Voltage Temperature Range 2.7V to 3.6V -40°C to 85°C 2.7V to 3.6V -40°C to 125°C 2.7V to 3.6V -40°C to 85°C 2.7V to 3.6V -40°C to 125°C 2.7V to 3.6V -40° ...
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... Min INDEX AREA PIN NO IDENT OPTION 02 0.300 – 0.320 (7.620 – 8.128) 0.065 (1.651) 95° ± 5° 0.008 – 0.016 TYP (0.203 – 0.406) 0.280 (7.112) MIN +0.040 0.325 –0.015 +1.016 8.255 –0.381 FMS7401L 78 ...
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... Seating Plane 0.014 - 0.020 Typ. (0.356 - 0.508) 0.335 - 0.344 (8.509 - 8.788 0.010 Max. (0.254 Typ. 0.004 - 0.010 (0.102 - 0.254) 0.014 - 0.020 Typ. (0.356 - 0.508) 0.008 Typ (0.203) FMS7401L 79 ...
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... FMS7401L †† Physical Dimensions 8-Pin TSSOP 0.246 - 0.256 (6.25 - 6.5) 0.123 - 0.128 (3.13 - 3.30) 0.0433 Max (1.1) 0.0256 (0.65) Typ. Notes: Unless otherwise specified 1. Reference JEDEC registration MO153. Variation AA. Dated 7/93 14-Pin TSSOP 6.4 3.2 1.1 Max TYP All Lead Tips - C - 0.65 Typ. Dimensions are in millimeters Notes: Unless otherwise specified 1. Reference JEDED registration MO153. Variation AB. ...
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... FMS7401L DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. ...