L64777 LSI Logic Corporation, L64777 Datasheet - Page 104

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L64777

Manufacturer Part Number
L64777
Description
DVB Qam Modulator
Manufacturer
LSI Logic Corporation
Datasheet
A-2
Figure A.1
At the serial interface, data transfers on the SDA pin are synchronized to
a serial clock input on the SCL line. The serial data clock can have a
maximum frequency of 400 kHz. The pins SB_BASE[1:0] input the two
LSB’s of the slave address required by the serial bus protocol. The slave
address definition is shown below:
The bus master always generates the clock and cycle start and stop
conditions. Figure A.2 gives an overview of the read and write cycles
using the serial bus protocol.
Programming the L64777 in Serial Host Interface Mode
Serial Bus Compliant Device
1
1
Quick Overview of the Serial Bus
7-Bit Slave Address for L64777 Serial Bus
0
1
Serial Bus Compliant Device
0
SB_BASE1 SB_BASE0
5 V
SCL
SDA

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