L64777 LSI Logic Corporation, L64777 Datasheet - Page 105

• Manufacturer Part Number: L64777
• Description: DVB Qam Modulator
• Manufacturer: LSI Logic Corporation

SDA
SDA
SDA
SCL
Figure A.2
Condition
Start
Start Condition: The master (which drives the SCL) indicates the start of a cycle by pulling SDA to LOW when
SCL is HIGH.
Stop Condition: The master (which drives the SCL) indicates the end of a cycle by releasing SDA to HIGH when
SCL is HIGH.
Data Transfer: All data changes on the SDA line happen only when clock is LOW, except for the special cases
outlined above to indicate cycle Start/Stop.
Acknowledge: The receiver always generates the acknowledge. In the case of a single read, the master-receiver
does not generate an ACK so that it can generate the Stop condition (as indicated above).
bit7
bit7
bit7
Serial Bus Write/Read Cycle
bit6
Master-Transmitter, Slave-Receiver
bit6
Master-Transmitter, Slave-Receiver
bit6
Master-Transmitter, Slave-Receiver
(Master transmits slave address)
(Master transmits slave address)
(Master transmits slave address)
bit5
bit5
bit5
Serial Bus Protocol Overview
bit4
bit4
bit4
bit3
bit3
bit3
bit2
bit2
bit2
bit1
bit1
bit1
R/W
Read Cycle (burst)
R/W
Single-Read Cycle
R/W
ACK Cycle: Slave
ACK Cycle: Slave
ACK Cycle: Slave
Write Cycle
bit7
bit7
bit7
bit6
bit6
bit6
Master-Transmitter, Slave-Receiver
Master-Receiver, Slave-Transmitter
Master-Receiver, Slave-Transmitter
(Slave transmits data to master)
(Slave transmits data to master)
(Master transmits data to slave)
bit5
bit5
bit5
bit4
bit4
bit4
bit3
bit3
bit3
bit2
bit2
bit2
bit1
bit1
bit1
ACK Cycle: Master
ACK Cycle: Master
bit0
ACK Cycle: Slave
bit0
bit0
Condition
Condition
Stop
Stop
bit7
A-3