L64777 LSI Logic Corporation, L64777 Datasheet - Page 86

• Manufacturer Part Number: L64777
• Description: DVB Qam Modulator
• Manufacturer: LSI Logic Corporation

5.5 Control Signals
5.6 External PLL Signals
5-6
TDI[7]
TCK[6]
OCLK
PLL_MODE[1:0]
RESET_n
PCLK
PLL_OUT_CS PLL Current Source
Signals
Test Data Input
TDI is the JTAG unit data input.
Test Mode Clock
TCK is the JTAG test mode clock.
Encoder Out/Processing Clock In
OCLK is a positive-edge-triggered clock. The L64777
internally processes data based on a fraction of OCLK
(for example: scrambler, interleaver, Reed-Solomon
encoder) and references data outputs (I, Q,
FSTARTOUT) to OCLK.
Select PLL Mode
To select the PLL mode:
0b00 or 0b01 for external PLL usage
0b11 for NCO usage
Reset
This pin resets all internal data paths. Reset timing is
asynchronous to the device clocks. Reset affects all the
configuration registers and the filter coefficients, which
must be downloaded again after reset.
Processing Clock: PLL Mode 2
The PCLK output of the L64724 provides this clock,
which drives the digital signal processing of interpolation
and the NCO. When using Mode 1, leave this pin open.
This pin is a charge pump for an external PLL low pass
to control frequency. The comparator is frequency- and
phase-sensitive. The pin is normally on 3-state Z level
and drives positive and negative current, as required.
Depending on the configuration, the current source can
be inverted.
3-State Output
Bidirectional
Input
Input
Input
Input
Input