FAN3224 Fairchild Semiconductor, FAN3224 Datasheet - Page 18

• Manufacturer Part Number: FAN3224
• Description: Dual 4A High-speed, Low-side Gate Drivers
• Manufacturer: Fairchild Semiconductor

© 2007 Fairchild Semiconductor Corporation
FAN3223 / FAN3224 / FAN3225 • Rev. 1.0.5
Truth Table of Logic Operation
The FAN3225 truth table indicates the operational states
using the dual-input configuration. In a non-inverting
driver configuration, the IN- pin should be a logic LOW
signal. If the IN- pin is connected to logic HIGH, a disable
function is realized, and the driver output remains LOW
regardless of the state of the IN+ pin.
In the non-inverting driver configuration in Figure 48,
the IN- pin is tied to ground and the input signal (PWM)
is applied to IN+ pin. The IN- pin can be connected to
logic HIGH to disable the driver and the output remains
LOW, regardless of the state of the IN+ pin.
In the inverting driver application in Figure 49, the IN+
pin is tied HIGH. Pulling the IN+ pin to GND forces the
output LOW, regardless of the state of the IN- pin.
PWM
IN+
PWM
Figure 48. Dual-Input Driver Enabled,
Figure 49. Dual-Input Driver Enabled,
0
0
1
1
Non-Inverting Configuration
Inverting Configuration
IN+
IN-
IN+
IN-
IN-
0
1
0
1
FAN3225
FAN3225
VDD
VDD
GND
GND
OUT
OUT
OUT
0
0
1
0
18
Operational Waveforms
At power-up, the driver output remains LOW until the
V
magnitude of the OUT pulses rises with V
steady-state
operation illustrated in Figure 50 shows that the output
remains LOW until the UVLO threshold is reached, then
the output is in-phase with the input.
For the inverting configuration of Figure 49, start-up
waveforms are shown in Figure 51. With IN+ tied to
VDD and the input signal applied to IN–, the OUT
pulses are inverted with respect to the input. At power-
up, the inverted output remains LOW until the V
voltage reaches the turn-on threshold, then it follows
the input with inverted phase.
(VDD)
DD
IN+
VDD
IN-
OUT
Figure 50. Non-Inverting Start-Up Waveforms
voltage reaches the turn-on threshold. The
Figure 51. Inverting Start-Up Waveforms
V
DD
is
reached.
The
Turn-on threshold
non-inverting
www.fairchildsemi.com
DD
until
DD