AD9116-EBZ Analog Devices, AD9116-EBZ Datasheet - Page 32

• Manufacturer Part Number: AD9116-EBZ
• Description: Dual, 8-/10-/12-/14-bit Low Power Digital-to-analog Converters
• Manufacturer: Analog Devices

AD9114/AD9115/AD9116/AD9117
MSB/LSB TRANSFERS
The serial port of the AD9114/AD9115/AD9116/AD9117 can
support both most significant bit (MSB) first or least significant
bit (LSB) first data formats. This functionality is controlled by the
LSBFIRST bit (Register 0x00, Bit 6). The default is MSB first
(LSBFIRST = 0).
When LSBFIRST = 0 (MSB first), the instruction and data bytes
must be written from the most significant bit to the least significant
bit. Multibyte data transfers in MSB first format start with an
instruction byte that includes the register address of the most
significant data byte. Subsequent data bytes should follow in
order from a high address to a low address. In MSB first mode,
the serial port internal byte address generator decrements for
each data byte of the multibyte communications cycle.
When LSBFIRST = 1 (LSB first), the instruction and data bytes
must be written from the least significant bit to the most signif-
icant bit. Multibyte data transfers in LSB first format start with
an instruction byte that includes the register address of the least
significant data byte followed by multiple data bytes. The serial
port internal byte address generator increments for each byte
of the multibyte communication cycle.
The serial port controller data address of the AD9114/AD9115/
AD9116/AD9117 decrements from the data address written
toward 0x00 for multibyte I/O operations if the MSB first mode
is active. The serial port controller address increments from the
data address written toward 0x1F for multibyte I/O operations
if the LSB first mode is active.
Rev. 0 | Page 32 of 48
SERIAL PORT OPERATION
The serial port configuration of the AD9114/AD9115/AD9116/
AD9117 is controlled by Register 0x00. It is important to note
that the configuration changes immediately upon writing to the
last bit of the register. For multibyte transfers, writing to this
register can occur during the middle of the communications
cycle. Care must be taken to compensate for this new configu-
ration for the remaining bytes of the current communications cycle.
The same considerations apply to setting the software reset,
RESET (Register 0x00, Bit 5). All registers are set to their default
values except Register 0x00, which remains unchanged.
Use of single-byte transfers or initiating a software reset is
recommended when changing serial port configurations to
prevent unexpected device behavior.
PIN MODE
The AD9114/AD9115/AD9116/AD9117 can also be operated
without ever writing to the serial port. With RESET/PINMD
(Pin 35) tied high, the SCLK pin becomes CLKMD to provide
for clock mode control (see the Retimer section), the SDIO
pin becomes FORMAT and selects the input data format, and
the former CS pin serves to power down the device.
Operation is otherwise exactly as defined by the default
register values in Table 14, so external resistors at FSADJI
and FSADJQ are needed to set the DAC currents, and both
DACs are active. This is also a convenient quick checkout mode.
DAC currents can be externally adjusted in pin mode by sourcing
or sinking currents at the FSADJI/AUXI and FASDJQ/AUXQ
pins as desired with the fixed resistors installed. An op amp
output with appropriate series resistance would be one of
many possibilities. This has the same effect as changing the
resistor value. Place at least 10 kΩ resistors in series right at
the DAC to guard against accidental short circuits and noise
modulation. The REFIO pin can be adjusted ±25% in a similar
manner, if desired.