AD9116-EBZ Analog Devices, AD9116-EBZ Datasheet - Page 44

• Manufacturer Part Number: AD9116-EBZ
• Description: Dual, 8-/10-/12-/14-bit Low Power Digital-to-analog Converters
• Manufacturer: Analog Devices

AD9114/AD9115/AD9116/AD9117
DIFFERENTIAL BUFFERED OUTPUT
USING AN OP AMP
A dual op amp (see the circuit shown in Figure 90) can be used
in a differential version of the single-ended buffer shown in
Figure 89. The same R-C network is used to form a one-pole
differential, low-pass filter to isolate the op amp inputs from
the high frequency images produced by the DAC outputs.
The feedback resistors, R
to-peak signal swing by the formula
The maximum and minimum single-ended voltages out of the
amplifier are, respectively,
The common-mode voltage of the differential output is
determined by the formula
AUXILIARY DACs
The DACs of the AD9114/AD9115/AD9116/AD9117 feature
two versatile and independent 10-bit auxiliary DACs suitable
for dc offset correction and similar tasks.
Because the AUXDACs are driven through the SPI port, they
should never be used in timing-critical applications, such
as inside analog feedback loops.
AD9114/AD9115/
AD9116/AD9117
V
V
V
V
OUT
MIN
CM
MAX
= V
= V
= 2 × R
=
V
MAX
MAX
REF
Figure 90. Single-Supply Differential Buffer
IOUTN
IOUTP
REFIO
AVSS
– R
FB
− R
×
× I
⎛
⎜ ⎜
⎝
FB
28
25
FB
34
29
1
× I
FS
+
× I
R
FB
FS
R
R
FS
FB
, determine the differential peak-
B
S
R
⎞
⎟ ⎟
⎠
S
C
R
R
B
B
ADA4841-2
ADA4841-2
–
+
+
–
R
R
C
C
FB
FB
F
F
V
OUT
Rev. 0 | Page 44 of 48
To keep the pin count reasonable, these auxiliary DACs each
share a pin with the corresponding FSADJx resistor. They are,
therefore, usable only when enabled and when that DAC is
operated on its internal full-scale resistors. A simple I-to-V
converter is implemented on chip with selectable shunt resistors
(3.2 kΩ to 16 kΩ) such that if REFIO is set to exactly 1 V, REFIO/2
equals 0.5 V and the following equation describes the no load
output voltage:
Figure 91 illustrates the function of all the SPI bits controlling
these DACs with the exception of the QAUXEN and IAUXEN
bits and gating to prohibit R
The SPI speed limits the update rate of the auxiliary DACs. The
data is inverted such that I
at 0x1FF, as shown in Figure 92.
RNG0
RNG1
Figure 92. AUXDAC Op Amp Output vs. Current, AVDD = 3.3 V No Load,
OFS2
OFS1
OFS0
V
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
OUT
0
AUXDAC
0
[9:0]
(OFS > 4 = 4)
=
4kΩ
10
0
Figure 91. AUXDAC Simplified Circuit Diagram
5 .
20
8kΩ
V
−
30
OP AMP OUTPUT VOLTAGE vs.
CHANGES IN R_OFFSET AND IDAC
16kΩ 16kΩ
⎛
⎜
⎜
⎝
I
AUXDAC 0x1FF to 0x000
DAC
40
AVDD
AUXDAC
50
−
REFIO
S
1
R
2
IDAC (µA)
< 3.2 kΩ.
5 .
60
S
⎞
⎟
⎟
⎠
16
is full scale at 0x000 and zero
70
RNG: 00 = 125µA
k
–
+
OP AMP
Ω
80
01 = 62µA
10 = 31µA
11 = 16µA
16kΩ
R_OFFSET = 3.3kΩ
R_OFFSET = 4kΩ
R_OFFSET = 5.3kΩ
R_OFFSET = 8kΩ
R_OFFSET = 16kΩ
90
100
f
f
f
S
S
S
f
S
110
120 130
AUX
PIN