LFEC10E-3F256C Lattice Semiconductor Corp., LFEC10E-3F256C Datasheet - Page 108

• Manufacturer Part Number: LFEC10E-3F256C
• Description: Latticeecp/ec Family of Fpga Devices Has Been Optimized to Deliver Mainstream Fpga Features at Low Cost.for Maximum Performance And Value, The Latticeecp (EConomy Plus) Fpga Concept Combines an Efficient Fpgafabric With High-speed Dedicated Functions
• Manufacturer: Lattice Semiconductor Corp.

© 2004 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other
brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without
notice.
May 2004
Introduction
This technical note discusses memory usage for the LatticeEC™ and LatticeECP™ device families. It is intended
to be used by design engineers as a guide in integrating the EBR and PFU based memories for these device fami-
lies in ispLEVER
The architecture of the LatticeECP/EC devices provides a large amount of resources for memory intensive applica-
tions. The sysMEM™ Embedded Block RAM (EBR) complements its distributed PFU-based memory. Single-Port
RAM, Dual-Port RAM, Pseudo Dual-Port RAM and ROM memories can be constructed using the EBR. LUTs and
PFU can implement Distributed Single-Port RAM, Dual-Port RAM and ROM. The internal logic of the device can be
used to configure the memory elements as FIFO and other storage types.
The capabilities of the EBR Block RAM and PFU RAM are referred to as primitives and described later in this doc-
ument. Designers can utilize the memory primitives in two separate ways:
The remainder of this document discusses these approaches, utilizing the Module Manager, PMI inference, mem-
ory modules and memory primitives.
Utilizing the Module Manager
Designers can utilize the Module Manager to easily specify a variety of memories in their designs. These modules
will be constructed using one or more memory primitives along with general purpose routing and LUTs as required.
The available modules are:
Module Manager Flow
For generating any of these memories, create (or open) a project for the LatticeEC or LatticeECP devices.
From the Project Navigator, select Tools > Module / IP Manager. Alternatively, users can also click on the button in
the toolbar when the LatticeECP/EC devices are targeted in the project.
This opens the Module Manager window as shown in Figure 8-1.
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• Via the Module Manager – The Module Manager GUI allows users to specify the memory type and size
• Via the PMI (Parameterizable Module Inferencing) – PMI allows experienced users to skip the graphical
• Single Port RAM (RAM_DQ) – EBR based
• Dual PORT RAM (RAM_DP_TRUE) – EBR based
• Pseudo Dual Port RAM (RAM_DP) – EBR based
• Read Only Memory (ROM) – EBR Based
• First In First Out Memory (FIFO and FIFO_DC) – EBR Based
• Distributed Single Port RAM (Distributed_SPRAM) – PFU based
• Distributed Dual Port RAM (Distributed_DPRAM) – PFU based
• Distributed ROM (Distributed_ROM) – PFU/PFF based
that is required. The Module Manager takes this specification and constructs a netlist to implement the
desired memory by using one or more of the memory primitives.
interface and utilize the Configurable memory modules on the fly from the ispLEVER Project Navigator. The
parameters and the control signals needed either in Verilog or VHDL can be set. The top-level design will
have the parameters defined and signals declared so the interface can automatically generate the black box
during synthesis.
®
.
8-1
Memory Usage Guide for
LatticeECP/EC Devices
Technical Note TN1051
tn1051_01