LFEC10E-3F256C Lattice Semiconductor Corp., LFEC10E-3F256C Datasheet - Page 221

• Manufacturer Part Number: LFEC10E-3F256C
• Description: Latticeecp/ec Family of Fpga Devices Has Been Optimized to Deliver Mainstream Fpga Features at Low Cost.for Maximum Performance And Value, The Latticeecp (EConomy Plus) Fpga Concept Combines an Efficient Fpgafabric With High-speed Dedicated Functions
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
With a sufficiently large SPI Flash, multiple FPGAs can be configured as shown in Figure 13-2. The first FPGA is
configured in SPI Mode, the following FPGAs are configured in Slave Serial Mode.
Figure 13-2. Multiple FPGA Configured by One SPI Flash
One FPGA, Two SPI Flash
The LatticeECP/EC devices support two Flash to configure a single device as shown in Figure 13-3. The two Flash
option is supported to allow use of smaller SPI Flash devices to configure a larger FPGA. Lattice’s ispVM
software divides the configuration bit stream evenly among each selected SPI memory. As the LatticeECP/EC
device starts to download from the two SPI memories, the data streams feed into D0 and D1 in a parallel fashion
and are reassembled internally.
Figure 13-3. Two SPI Flash
SPIX Mode
Not all SPI memories are the same. A read operation code is required to be fed to the SPI Flash at the time config-
uration starts. For many, that op code is 03 Hex. For other memories that require a different read operation code
other than 03 Hex, the SPIX format is supported. In SPIX mode the read operation code is coded into the D[0:7]
SPIX
RESET (optional)
SPI3 Flash
Mode
SCK
CS
SO
SI
CCLK
DI/CSSPIN
BUSY
D0
Lattice FPGA
SCK
CS
SI
SCK
CS
SI
SPI3
CFG[2]
SPI3 Flash 0
SPI3 Flash 1
0
CFG0
DOUT
CFG2
CFG1
SO
SO
CFG[1]
13-7
DI/CSSPIN
CCLK
0
NC
Lattice FPGA
Slave Serial
Lattice ECP/EC sysCONFIG Usage Guide
CCLK
DI/CSSPIN
BUSY
D0
D1
D[2:7]
PROGRAMN
Lattice FPGA
CFG[0]
DOUT
1
CFG2
CFG1
CFG0
SPI3
CFG0
CFG2
CFG1
SPIX
CCLK
DI/CSSPIN
CONFIG_MODE Parameter
Lattice FPGA
Slave Serial
DOUT
CFG2
CFG1
CFG0
®
System