LFEC10E-3F256C Lattice Semiconductor Corp., LFEC10E-3F256C Datasheet - Page 136

• Manufacturer Part Number: LFEC10E-3F256C
• Description: Latticeecp/ec Family of Fpga Devices Has Been Optimized to Deliver Mainstream Fpga Features at Low Cost.for Maximum Performance And Value, The Latticeecp (EConomy Plus) Fpga Concept Combines an Efficient Fpgafabric With High-speed Dedicated Functions
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
IDDRXB
This primitive will implement the input register block. The software defaults to CE Enabled unless otherwise speci-
fied. The ECLK input is used to connect to the DQS strobe coming from the DQS delay block (DQSBUFB primitive).
The SCLK input should be connected to the system (FPGA) clock. The SCLK and CE inputs to this primitive will be
used primarily to synchronize the DDR inputs. DDRCLKPOL is an input from the DQS Clock Polarity tree. This sig-
nal is generated by the DQS Transition detect circuit in the hardware. Figure 9-7 shows the primitive symbol and
the I/O ports.
Figure 9-7. IDDRXB Symbol
Table 9-4 provides a description of all I/O ports associated with the IDDRXB primitive.
Table 9-4. IDDRXB Ports
Note:
1. The DDRCLKPOL input to IDDRXB should be connected to the DDRCLKPOL output of DQSBUFB.
D
ECLK
LSR
SCLK
CE
DDRCLKPOL
QA
QB
Port Name
I/O
O
O
I
I
I
I
I
I
DDR data
The phase shifted DQS should be connected to this input
Reset
System CLK
Clock enable
DDR clock polarity signal
Data at Positive edge of the CLK
Data at the negative edge of the CLK
D
ECLK
LSR
SCLK
CE
DDRCLKPOL
IDDRXB
9-7
Definition
QA
QB
Lattice ECP/EC DDR Usage Guide