LFEC10E-3F256C Lattice Semiconductor Corp., LFEC10E-3F256C Datasheet - Page 213

• Manufacturer Part Number: LFEC10E-3F256C
• Description: Latticeecp/ec Family of Fpga Devices Has Been Optimized to Deliver Mainstream Fpga Features at Low Cost.for Maximum Performance And Value, The Latticeecp (EConomy Plus) Fpga Concept Combines an Efficient Fpgafabric With High-speed Dedicated Functions
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
second node is switching every other clock rising edge that corresponds to an Activity Factor of 1/2. The third node
is switching every fourth clock rising edge for an Activity Factor of 1/4. The series for the sequence of 16 nodes is 1
+ 1/2 + 1/4 + 1/8 + 1/16 + ... + 1/215 converges to 2. Assuming a sum of 2 for the counter, divide by the total num-
ber of nodes (16) to measure the average AF per counter of 2/16 = 0.125.
Ambient and Junction Temperature and Airflow
A common method of characterizing a packaged device’s thermal performance is with thermal resistance, Θ. For a
semiconductor device, thermal resistance indicates the steady state temperature rise of the die junction above a
given reference for each watt of power (heat) dissipated at the die surface. Its units are °C/W.
The most common examples are Θ
tance junction-to-case (also in °C/W). Another factor is Θ
Knowing the reference (i.e. ambient, case or board) temperature, the power, and the relevant Θ value, the junction
temperature can be calculated as per following equations.
Where T
P is the total power dissipation of the device.
Θ
a high conductivity case mounted directly to a PCB or heatsink. And Θ
cent to the package is known.
Power Calculator utilizes the Ambient Temperature (°C) to calculate the junction temperature (°C) based on the Θ
for the targeted device, per Equation 1 above. Users can also provide the airflow values (in LFM) to get a more
accurate value of the junction temperature.
Managing Power Consumption
There are several design techniques that FPGA designers can use to reduce overall FPGA power consumption or
reduce its impact on junction temperature. Some of these are:
JA
is commonly used with natural and forced convection air-cooled systems. Θ
1. Reducing operating voltage. For example, operating at the low end of the voltage range allowed, given
2. Optimizing the clock frequency. Often clock rate can be reduced, for all or some portions of the design.
3. Reducing the span of the design across the device. A more closely placed design utilizes less routing
4. Reducing the voltage swing of the I/Os where possible. A double-ended LVDS has much less voltage
5. Using optimum encoding where possible. For example, a 16-bit binary counter has, on average, only a
T
T
T
the nominal voltage chosen.
resources and hence less power consumption.
swing as compared to single-ended CMOS.
12% Activity Factor while a 7-bit binary counter has an average of 28% Activity Factor. On the other hand,
a 7-bit LFSR counter will toggle at an Activity factor of 50%, which causes higher power consumption. A
gray code counter, where only one bit changes at each clock edge, will use the least amount of power, with
an Activity Factor of less than 10%.
J
, T
J
J
J
= T
= T
= T
A,
T
A
C
B
C
+ Θ
+ Θ
+ Θ
and T
JA
JC
JB
* P
* P
* P
B
are the junction, ambient, case (or package) and board temperatures (in °C) respectively.
(1)
(2)
(3)
JA
, thermal resistance junction-to-ambient (in °C/W) and Θ
12-17
Estimating Power Using the Power Calculator
JB
, thermal resistance junction-to-board (in °C/W).
JB
applies when the board temperature adja-
JC
for LatticeECP/EC Devices
is useful when the package has
JC
, thermal resis-
JA