LFEC10E-3F256C Lattice Semiconductor Corp., LFEC10E-3F256C Datasheet - Page 125

• Manufacturer Part Number: LFEC10E-3F256C
• Description: Latticeecp/ec Family of Fpga Devices Has Been Optimized to Deliver Mainstream Fpga Features at Low Cost.for Maximum Performance And Value, The Latticeecp (EConomy Plus) Fpga Concept Combines an Efficient Fpgafabric With High-speed Dedicated Functions
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Figure 8-17. Distributed Dual Port RAM Module Generated by the Module Manager
The generated module makes use of a 4-input LUT available in the PFU. Additional logic like Clock and Reset is
generated by utilizing the resources available in the PFU. The basic Distributed Dual Port RAM primitive for the Lat-
ticeECP/EC devices is shown in Figure 8-18.
Figure 8-18. PFU-based Distributed Dual Port RAM for Lattice-EC/ECP Devices
Ports such as Read Clock (RdClock) and Read Clock Enable (RdClockEn) are not available in the hardware primi-
tive. These are generated by the Module Manager when the user wants the to enable the output registers in the
Module Manager configuration.
The various ports and their definitions for the memory are included in Table 8-15. The table lists the corresponding
ports for the module generated by Module Manager and for the primitive.
WAD[3:0]
RAD[3:0]
DI[1:0]
RdClockEn
WrClockEn
WrAddress
RdAddress
WCK
WRE
RdClock
WrClock
Reset
Data
WE
Distributed Single Port
PFU
8-18
PFU based
Memory
WDO[1:0]
RDO[1:0]
Q
for LatticeECP/EC Devices
Memory Usage Guide for