LFEC10E-3F256C Lattice Semiconductor Corp., LFEC10E-3F256C Datasheet - Page 21

• Manufacturer Part Number: LFEC10E-3F256C
• Description: Latticeecp/ec Family of Fpga Devices Has Been Optimized to Deliver Mainstream Fpga Features at Low Cost.for Maximum Performance And Value, The Latticeecp (EConomy Plus) Fpga Concept Combines an Efficient Fpgafabric With High-speed Dedicated Functions
• Manufacturer: Lattice Semiconductor Corp.

Lattice Semiconductor
Figure 2-11. sysMEM EBR Primitives
The EBR memory supports three forms of write behavior for single port or dual port operation:
1. Normal – data on the output appears only during read cycle. During a write cycle, the data (at the current
2. Write Through – a copy of the input data appears at the output of the same port, during a write cycle.
3. Read-Before-Write – when new data is being written, the old content of the address appears at the output.
Memory Core Reset
The memory array in the EBR utilizes latches at the A and B output ports. These latches can be reset asynchro-
nously or synchronously. RSTA and RSTB are local signals, which reset the output latches associated with Port A
and Port B respectively. The Global Reset (GSRN) signal resets both ports. The output data latches and associated
resets for both ports are as shown in Figure 2-12.
address) does not appear on the output.
AD[12:0]
AD[12:0]
DI[35:0]
CS[2:0]
CS[2:0]
RST
RST
CLK
CLK
WE
CE
CE
Single Port RAM
ROM
EBR
EBR
DO[35:0]
DO[35:0]
2-11
ADW[12:0]
DOA[17:0]
ADA[12:0]
DIA[17:0]
CSA[2:0]
DI[35:0]
CS[2:0]
CLKW
CLKA
RSTA
CEW
WEA
CEA
RST
WE
Pseudo-Dual Port RAM
True Dual Port RAM
EBR
EBR
LatticeECP/EC Family Data Sheet
ADB[12:0]
DIB[17:0]
CEB
CLKB
RSTB
WEB
CSB[2:0]
DOB[17:0]
ADR[12:0]
DO[35:0]
CER
CLKR
Architecture