HY27UH164G2M Hynix Semiconductor, HY27UH164G2M Datasheet

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Document Title 4Gbit (512Mx8bit / 256Mx16bit) NAND Flash Memory Revision History Revision No. 0.0 1) Add Errata tCLS Specification 0 Relaxed value 5 Case Specification Read(all) 0.1 Except for Relaxed value ID Read ID Read 2) Add note.4(table14) 3) Add ...

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FEATURES SUMMARY HIGH DENSITY NAND FLASH MEMORIES - Cost effective solutions for mass storage applications NAND INTERFACE - x8 or x16 bus width. - Multiplexed Address/ Data - Pinout compatibility for all densities SUPPLY VOLTAGE - 3.3V device: VCC = ...

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... This device includes also extra features like OTP/Unique ID area, Automatic Read at Power Up, Read ID2 extension. The HYNIX HY27(U/S)H(08/16)4G2M series is available TSOP1 mm. 1.1 Product List PART NUMBER HY27SH084G2M HY27SH164G2M HY27UH084G2M HY27UH164G2M Rev 0.1 / Feb. 2005 HY27UH(08/16)4G2M Series HY27SH(08/16)4G2M Series 4Gbit (512Mx8bit / 256Mx16bit) NAND Flash ORIZATION VCC RANGE x8 1 ...

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IO15 - IO8 IO7 - IO0 CLE ALE CE# RE# WE# WP# RB# Vcc Vss NC PRE Rev 0.1 / Feb. 2005 HY27UH(08/16)4G2M Series HY27SH(08/16)4G2M Series 4Gbit (512Mx8bit / 256Mx16bit) NAND Flash Figure1: Logic Diagram Data Input / Outputs (x16 ...

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Figure 2. 48TSOP1 Contactions, x8 and x16 Device Rev 0.1 / Feb. 2005 HY27UH(08/16)4G2M Series HY27SH(08/16)4G2M Series 4Gbit (512Mx8bit / 256Mx16bit) NAND Flash Preliminary 5 ...

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PIN DESCRIPTION Pin Name DATA INPUTS/OUTPUTS IO0-IO7 The IO pins allow to input command, address and data and to output data during read / program IO8-IO15(1) operations. The inputs are latched on the rising edge of Write Enable (WE#). ...

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IO0 1st Cycle A0 2nd Cycle A8 3rd Cycle A12 4th Cycle A20 5th Cycle A28 IO0 1st Cycle A0 2nd Cycle A8 3rd Cycle A11 4th Cycle A19 5th Cycle A27 FUNCTION READ 1 READ FOR COPY-BACK READ ID ...

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CLE ALE CE ( NOTE: 1. With ...

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BUS OPERATION There are six standard bus operations that control the device. These are Command Input, Address Input, Data Input, Data Output, Write Protect, and Standby. Typically glitches less than Chip Enable, Write Enable and Read ...

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DEVICE OPERATION 3.1 Page Read. Upon initial device power up, the device defaults to Read mode. This operation is also initiated by writing 00h and 30h to the command register along with four address cycles. In two consecutive read ...

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Block Erase. The Erase operation is done on a block basis. Block address loading is accomplished in three cycles initiated by an Erase Setup command (60h). Only address A18 to A29 (X8) or A17 to A28 (X16) is valid ...

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Read ID. The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of 00h. Four read cycles sequentially output the manufacturer code (ADh), and the device code and 00h, ...

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Cache Read Cache read operation allows automatic download of consecutive pages the whole device. Immediately after 1st latency end, while user can start reading out data, device internally starts reading following page. Start address of 1st page ...

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OTHER FEATURES 4.1 Data Protection. The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever Vcc is below about 1.5V. WP# pin provides hardware protection and is recommended ...

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Symbol Ambient Operating Temperature (Commercial Temperature Range) T Ambient Operating Temperature (Extended Temperature Range) A Ambient Operating Temperature (Industrial Temperature Range) T Temperature Under Bias BIAS T Storage Temperature STG (2) Input or Output Voltage V IO Vcc Supply Voltage ...

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Rev 0.1 / Feb. 2005 HY27UH(08/16)4G2M Series HY27SH(08/16)4G2M Series 4Gbit (512Mx8bit / 256Mx16bit) NAND Flash Figure 3: Block Diagram Preliminary 16 ...

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Parameter Symbol Sequential I CC1 Read Operating Current Program I CC2 Erase I CC3 Stand-by Current (TTL) I CC4 Stand-by Current (CMOS) I CC5 Input Leakage Current I LI Output Leakage Current I LO Input High Voltage V IH Input ...

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Item Input / Output Capacitance (1) Input Capacitance(1) Table 11: Pin Capacitance (TA=25C, F=1.0MHz) Note: 1. For the stacked devices version the Input Capacitance is <TBD> and the I/O capacitance is <TBD> Parameter Program Time Dummy Busy Time for Cache ...

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Parameter CLE Setup time CLE Hold time CE# setup time CE# hold time WE# pulse width ALE setup time ALE hold time Data setup time Data hold time Write Cycle time WE# High hold time ALE to Data Loading time ...

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Pagae Block IO Program Erase 0 Pass / Fail Pass / Fail Ready/Busy Ready/Busy 6 Ready/Busy Ready/Busy 7 Write Protect Write Protect DEVICE IDENTIFIER BYTE 1st 2nd ...

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Description 1K Page Size 2K (Without Spare Area) Reserved Reserved Spare Area Size 8 (Byte / 512Byte) 16 Standard (50ns) Serial Access Time Fast 64K Block Size 128K (Without Spare Area) 256K Reserved X8 Organization X16 Not Used Table 16: ...

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Rev 0.1 / Feb. 2005 4Gbit (512Mx8bit / 256Mx16bit) NAND Flash Figure 4: Command Latch Cycle Figure 5: Address Latch Cycle Preliminary HY27UH(08/16)4G2M Series HY27SH(08/16)4G2M Series 22 ...

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Figure 7: Sequential Out Cycle after Read (CLE=L, WE#=H, ALE=L) Rev 0.1 / Feb. 2005 HY27UH(08/16)4G2M Series HY27SH(08/16)4G2M Series 4Gbit (512Mx8bit / 256Mx16bit) NAND Flash Figure 6. Input Data Latch Cycle Preliminary 23 ...

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Rev 0.1 / Feb. 2005 4Gbit (512Mx8bit / 256Mx16bit) NAND Flash Figure 8: Status Read Cycle Figure 9: Read1 Operation (Read One Page) Preliminary HY27UH(08/16)4G2M Series HY27SH(08/16)4G2M Series 24 ...

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Figure 10: Read1 Operation intercepted by CE# Rev 0.1 / Feb. 2005 HY27UH(08/16)4G2M Series HY27SH(08/16)4G2M Series 4Gbit (512Mx8bit / 256Mx16bit) NAND Flash Preliminary 25 ...

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Rev 0.1 / Feb. 2005 4Gbit (512Mx8bit / 256Mx16bit) NAND Flash Figure 11 : Random Data output Preliminary HY27UH(08/16)4G2M Series HY27SH(08/16)4G2M Series 26 ...

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Rev 0.1 / Feb. 2005 4Gbit (512Mx8bit / 256Mx16bit) NAND Flash Figure 12: Page Program Operation Preliminary HY27UH(08/16)4G2M Series HY27SH(08/16)4G2M Series 27 ...

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Rev 0.1 / Feb. 2005 HY27UH(08/16)4G2M Series HY27SH(08/16)4G2M Series 4Gbit (512Mx8bit / 256Mx16bit) NAND Flash Figure 13 : Random Data In Preliminary 28 ...

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Rev 0.1 / Feb. 2005 4Gbit (512Mx8bit / 256Mx16bit) NAND Flash Figure 14 : Copy Back Program Preliminary HY27UH(08/16)4G2M Series HY27SH(08/16)4G2M Series 29 ...

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Rev 0.1 / Feb. 2005 HY27UH(08/16)4G2M Series HY27SH(08/16)4G2M Series 4Gbit (512Mx8bit / 256Mx16bit) NAND Flash Figure 15 : Cache Program Preliminary 30 ...

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Figure 16: Block Erase Operation (Erase One Block) Rev 0.1 / Feb. 2005 HY27UH(08/16)4G2M Series HY27SH(08/16)4G2M Series 4Gbit (512Mx8bit / 256Mx16bit) NAND Flash Figure 17: Read ID Operation Preliminary 31 ...

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Figure 18: start address at page start :after 1st latency uninterrupted data flow Figure 19: exit from cache read in 5ms when device internally is reading Rev 0.1 / Feb. 2005 HY27UH(08/16)4G2M Series HY27SH(08/16)4G2M Series 4Gbit (512Mx8bit / 256Mx16bit) NAND ...

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Figure 20: Page Read with CE# Don’t Care Option Rev 0.1 / Feb. 2005 HY27UH(08/16)4G2M Series HY27SH(08/16)4G2M Series 4Gbit (512Mx8bit / 256Mx16bit) NAND Flash Preliminary 33 ...

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Rev 0.1 / Feb. 2005 4Gbit (512Mx8bit / 256Mx16bit) NAND Flash Figure 21: Automatic Read at Power On Figure 22: Reset Operation Preliminary HY27UH(08/16)4G2M Series HY27SH(08/16)4G2M Series 34 ...

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Figure 23: Power On and Data Protection Timing VTH = 1.6 Volt for 1.8 Volt Supply devices; 2.5 Volt for 3.3 Volt Supply devices Rev 0.1 / Feb. 2005 HY27UH(08/16)4G2M Series HY27SH(08/16)4G2M Series 4Gbit (512Mx8bit / 256Mx16bit) NAND Flash Preliminary ...

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Figure 24: Ready/Busy Pin electrical specifications Rev 0.1 / Feb. 2005 HY27UH(08/16)4G2M Series HY27SH(08/16)4G2M Series 4Gbit (512Mx8bit / 256Mx16bit) NAND Flash Preliminary 36 ...

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Figure 25: page programming within a block Rev 0.1 / Feb. 2005 HY27UH(08/16)4G2M Series HY27SH(08/16)4G2M Series 4Gbit (512Mx8bit / 256Mx16bit) NAND Flash Preliminary 37 ...

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Bad Block Management Devices with Bad Blocks have the same quality level and the same AC and DC characteristics as devices where all the blocks are valid. A Bad Block does not affect the performance of valid blocks because it ...

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APPENDIX : Extra Features 5.1 Automatic Page0 Read after Power Up The timing diagram related to this operation is shown in Fig. 21 Due to this functionality the CPU can directly download the boot loader from the first page ...

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Figure 27. 48-TSOP1 - 48-lead Plastic Thin Small Outline 20mm, Package Outline Symbol alpha Table 19: 48-TSOP1 - 48-lead Plastic Thin Small Outline, Rev 0.1 / Feb. ...

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Application Note 1. Power-on/off Sequence After power is on, the device starts an internal circuit initialization when the power supply voltage reaches a specific level. The device shows its internal initialization status with the Ready/Busy signal if initialization is on ...

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Automatic sleep mode for low power consumption The device provides the automatic sleep function for low power consumption. The device enters the automatic sleep mode by keeping CE# at VIH level for 10us without any additional command input, and ...