HY27UH164G2M Hynix Semiconductor, HY27UH164G2M Datasheet - Page 19

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HY27UH164G2M

Manufacturer Part Number
HY27UH164G2M
Description
(HY27xHxx4G2M Series) 4G-Bit NAND Flash Memory
Manufacturer
Hynix Semiconductor
Datasheet
Rev 0.1 / Feb. 2005
CLE Setup time
CLE Hold time
CE# setup time
CE# hold time
WE# pulse width
ALE setup time
ALE hold time
Data setup time
Data hold time
Write Cycle time
WE# High hold time
ALE to Data Loading time
Data Transfer from Cell to register
ALE to RE# Delay (ID Read)
CLE to RE# Delay
Ready to RE# Low
RE# Pulse Width
WE# High to Busy
Read Cycle Time
RE# Access Time
RE# High to Output High Z
CE# High to Output High Z
RE# High Hold Time
Output High Z to RE# low
CE# Access Time
WE# High to RE# low
Device Resetting Time (Read / Program / Erase)
NOTE:
1. If t
2. The time to Ready depends on the value of the pull-up resistor tied to RB# pin
3. If Reset Command (FFh) is written at Ready state, the device goes into Busy for maximum 5us
4. These parameters are applied to the errata.
5. tADL is the time from the WE# rising edge of final address cycle to the WE# rising edge of first data cycle.
CS
is less than 10ns t
Parameter
WP
must be minimum 45ns, otherwise, t
Table 13: AC Timing Characteristics
4Gbit (512Mx8bit / 256Mx16bit) NAND Flash
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
CLH
ALH
ADL
REA
REH
CLS
ALS
t
WP
WC
t
t
t
DS
t
RP
RC
t
t
t
t
t
WHR
t
t
t
t
R
CLR
RHZ
CHZ
t
CEA
RST
WH
WB
CH
DH
CS
AR
RR
IR
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(5)
(4)
(4)
25
Min
10
10
10
20
15
50
20
10
10
20
25
50
20
60
WP
0
0
0
0
(1)
may be minimum 35ns.
1.8Volt
HY27UH(08/16)4G2M Series
5/10/500
HY27SH(08/16)4G2M Series
Max
100
100
25
30
30
20
45
(3)
25
Min
10
10
10
20
15
50
20
10
10
20
25
50
20
60
0
0
0
0
(1)
3.3Volt
5/10/500
Preliminary
Max
100
100
25
30
30
20
45
(3)
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
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