MT58L64V36P Micron Semiconductor, MT58L64V36P Datasheet - Page 17

• Manufacturer Part Number: MT58L64V36P
• Description: (MT58LxxxxP) 2Mb SRAM
• Manufacturer: Micron Semiconductor

NOT RECOMENDED FOR NEW DESIGNS
WRITE TIMING PARAMETERS
NOTE: 1. D(A2) refers to input for address A2. Q(A2 + 1) refers to input for the next internal burst address following A2.
2Mb: 128K x 18, 64K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L128L18P_C.p65 – Rev. C, Pub. 11/02
SYMBOL
t
f
t
t
t
t
t
t
t
KC
KH
OEHZ
AS
ADSS
AAS
KF
KL
WS
BWa#-BWd#
ADDRESS
(NOTE 2)
2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH.
3. OE# must be HIGH before the input data setup and held HIGH throughout the data hold time. This prevents
4. ADV# must be HIGH to permit a WRITE to the loaded address.
5. Full-width WRITE can be initiated by GW# LOW; or GW# HIGH and BWE#, BWa# and BWb# LOW for x18 device;
BWE#,
ADSP#
ADSC#
ADV#
GW#
OE#
CLK
CE#
When CE# is HIGH, CE2# is HIGH and CE2 is LOW.
input/output data contention for the time period prior to the byte write enable inputs being sampled.
or GW# HIGH and BWE#, BWa#-BWd# LOW for x32 and x36 devices.
MIN MAX MIN MAX MIN MAX MIN MAX UNITS
Q
D
5.0
1.6
1.6
1.5
1.5
1.5
1.5
-5
200
BURST READ
3.0
High-Z
6.0
1.7
1.7
1.5
1.5
1.5
1.5
t ADSS
t CES
t AS
-6
A1
t ADSH
166
3.5
t CEH
t AH
t KH
t OEHZ
(NOTE 3)
Byte write signals are
ignored for first cycle when
ADSP# initiates burst.
t KC
t ADSS
t KL
Single WRITE
7.5
1.9
1.9
1.5
1.5
1.5
1.5
t DS
D(A1)
-7.5
t ADSH
t DH
133
4.0
A2
3.2
3.2
2.2
2.2
2.2
2.2
10
-10
(NOTE 4)
100
4.5
D(A2)
WRITE TIMING
MHz
ns
ns
ns
ns
ns
ns
ns
ns
D(A2 + 1)
(NOTE 1)
t WS
BURST WRITE
17
PIPELINED, SCD SYNCBURST SRAM
t WH
(NOTE 5)
D(A2 + 1)
SYMBOL
t
t
t
t
t
t
t
t
DS
CES
AH
ADSH
AAH
WH
DH
CEH
ADV# suspends burst.
2Mb: 128K x 18, 64K x 32/36
D(A2 + 2)
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MIN MAX MIN MAX MIN MAX MIN MAX UNITS
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
-5
ADSC# extends burst.
D(A2 + 3)
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
-6
t ADSS
A3
D(A3)
t ADSH
DON’T CARE
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
Extended BURST WRITE
-7.5
t WS
t AAS
D(A3 + 1)
t AAH
t WH
©2002, Micron Technology, Inc.
2.2
2.2
0.5
0.5
0.5
0.5
0.5
0.5
UNDEFINED
-10
D(A3 + 2)
ns
ns
ns
ns
ns
ns
ns
ns