MT58L64V36P Micron Semiconductor, MT58L64V36P Datasheet - Page 6

• Manufacturer Part Number: MT58L64V36P
• Description: (MT58LxxxxP) 2Mb SRAM
• Manufacturer: Micron Semiconductor

NOT RECOMENDED FOR NEW DESIGNS
TQFP PIN DESCRIPTIONS (continued)
2Mb: 128K x 18, 64K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L128L18P_C.p65 – Rev. C, Pub. 11/02
62, 63, 68, 69, 56-59, 62, 63
14, 15, 41, 65, 14, 15, 41, 65,
26, 40, 55, 60, 26, 40, 55, 60,
66, 75, 78, 79,
13, 18, 19, 22, 72-75, 78, 79
54, 61, 70, 77 54, 61, 70, 77
67, 71, 76, 90 67, 71, 76, 90
38, 39, 42, 43 38, 39, 42, 43
51-53, 56, 57,
4, 11, 20, 27, 4, 11, 20, 27,
5, 10, 17, 21, 5, 10, 17, 21,
1-3, 6, 7, 16,
(b)
(a)
25, 28-30,
95, 96
72, 73
8, 9, 12,
x18
58, 59,
85
31
64
23
74
24
91
50
–
–
22-25, 28, 29
(c)
(a)
(b)
(d)
x32/x36
16, 66
12, 13
2, 3, 6-9,
52, 53,
68, 69,
18, 19,
85
31
64
51
80
30
91
50
1
SYMBOL
NC/DQPa
NC/DQPb
NC/DQPd
NC/DQPc
ADSC#
MODE
NC/SA
V
DQa
DQb
DQd
DQc
DNU
V
V
NC
ZZ
DD
DD
SS
Q
Output DQa pins; Byte “b” is associated with DQb pins. For the x32 and x36
Supply Power Supply: See DC Electrical Characteristics and Operating
Supply Isolated Output Buffer Supply: See DC Electrical Characteristics and
Supply Ground: GND.
Input/ SRAM Data I/Os: For the x18 version, Byte “a” is associated with
TYPE
Input
Input
Input
NC/
I/O
–
–
–
Synchronous Address Status Controller: This active LOW input
interrupts any ongoing burst, causing a new external address to be
registered. A READ or WRITE is performed using the new address if
CE# is LOW. ADSC# is also used to place the chip into power-down
state when CE# is HIGH.
Mode: This input selects the burst sequence. A LOW on this pin
selects “linear burst.” NC or HIGH on this pin selects “interleaved
burst.” Do not alter input state while device is operating.
Snooze Enable: This active HIGH, asynchronous input causes the
device to enter a low-power standby mode in which all data in the
memory array is retained. When ZZ is active, all other inputs are
ignored.
versions, Byte “a” is associated with DQa pins; Byte “b” is
associated with DQb pins; Byte “c” is associated with DQc pins;
Byte “d” is associated with DQd pins. Input data must meet setup
and hold times around the rising edge of CLK.
No Connect/Parity Data I/Os: On the x32 version, these pins are No
Connect (NC). On the x18 version, Byte “a” parity is DQPa; Byte “b”
parity is DQPb. On the x36 version, Byte “a” parity is DQPa; Byte
“b” parity is DQPb; Byte “c” parity is DQPc; Byte “d” parity is DQPd.
Conditions for range.
Operating Conditions for range.
Do Not Use: These signals may either be unconnected or wired to
GND to improve package heat dissipation.
No Connect: These signals are not internally connected and may be
connected to ground to improve package heat dissipation.
No Connect: This pin is reserved for address expansion.
6
PIPELINED, SCD SYNCBURST SRAM
2Mb: 128K x 18, 64K x 32/36
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DESCRIPTION
©2002, Micron Technology, Inc.