MT58L64V36P Micron Semiconductor, MT58L64V36P Datasheet - Page 3

• Manufacturer Part Number: MT58L64V36P
• Description: (MT58LxxxxP) 2Mb SRAM
• Manufacturer: Micron Semiconductor

NOT RECOMENDED FOR NEW DESIGNS
GENERAL DESCRIPTION (continued)
simplify WRITE cycles. This allows self-timed WRITE
cycles. Individual byte enables allow individual bytes
to be written. During WRITE cycles on the x18 device,
BWa# controls DQa pins and DQPa; BWb# controls
DQb pins and DQPb. During WRITE cycles on the x32
and x36 devices, BWa# controls DQa pins and DQPa;
BWb# controls DQb pins and DQPb; BWc# controls
DQc pins and DQPc; BWd# controls DQd pins and
DQPd. GW# LOW causes all bytes to be written. Parity
pins are only available on the x18 and x36 versions.
ture during READ cycles. If the device is immediately
TQFP PIN ASSIGNMENT TABLE
*Pin 50 is reserved for address expansion.
**No Connect (NC) is used on the x32 version. Parity (DQPx) is used on the x36 version.
2Mb: 128K x 18, 64K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L128L18P_C.p65 – Rev. C, Pub. 11/02
PIN #
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
1
2
3
4
5
6
7
8
9
Address and write control are registered on-chip to
This device incorporates a single-cycle deselect fea-
DQPb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
x18
NC
NC
NC
NC
NC
NC
V
V
V
V
V
V
V
V
V
NC
DD
DD
DD
DD
DD
S S
S S
S S
S S
NC/DQPc**
Q
Q
Q
x32/x36
DQd
DQd
DQd
DQd
DQd
DQd
DQc
DQc
DQc
DQc
DQc
DQc
DQc
DQc
PIN #
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
x18
NC
NC
NC
NC/SA*
MODE
V
DNU
DNU
DNU
DNU
SA1
SA0
V
V
V
SA
SA
SA
SA
SA
SA
SA
SA
SA
SA
DD
DD
S S
S S
NC/DQPd**
Q
x32/x36
DQd
DQd
3
PIPELINED, SCD SYNCBURST SRAM
deselected after a READ cycle, the output bus goes to a
High-Z state
of clock.
+3.3V V
TTL-compatible. Users can choose either a 3.3V or 2.5V
I/O version. The device is ideally suited for Pentium and
PowerPC pipelined systems and systems that benefit
from a very wide, high-speed data bus. The device is also
ideal in generic 16-, 18-, 32-, 36-, 64-, and 72-bit-wide
applications.
sramds) for the latest data sheet.
PIN #
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
Micron’s 2Mb SyncBurst SRAMs operate from a
Please refer to Micron’s Web site
2Mb: 128K x 18, 64K x 32/36
DQPa
DD
DQa
DQa
DQa
DQa
x18
NC
NC
NC
NC
NC
NC
Micron Technology, Inc., reserves the right to change products or specifications without notice.
power supply, and all inputs and outputs are
V
V
V
DQa
DQa
DQa
DQa
V
t
V
V
V
V
NC
DD
DD
ZZ
DD
KQHZ nanoseconds after the rising edge
DD
S S
S S
S S
S S
NC/DQPa**
Q
Q
Q
x32/x36
DQa
DQa
DQa
DQa
DQb
DQb
DQb
DQb
DQb
DQb
PIN #
100
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
(www.micron.com/
x18
NC
NC
SA
NC
NC
©2002, Micron Technology, Inc.
ADSP#
ADSC#
BWE#
BWa#
BWb#
V
ADV#
GW#
CE2#
OE#
CLK
V
CE2
CE#
V
V
SA
SA
SA
SA
DD
DD
S S
S S
NC/DQPb**
Q
x32/x36
BWd#
BWc#
DQb
DQb