MT58V512V36D Micron Technology, MT58V512V36D Datasheet - Page 20

• Manufacturer Part Number: MT58V512V36D
• Description: (MT58xxxx) 16Mb SYNCBURST SRAM
• Manufacturer: Micron Technology

READ TIMING PARAMETERS
NOTE: 1. Q(A2) refers to output from address A2. Q(A2 + 1) refers to output from the next internal burst address following A2.
16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM
MT58L1MY18D_2.p65 – Rev 7/00
GW#, BWE#,
BWa#-BWd#
SYM
t
f
t
t
t
t
t
t
t
t
t
KC
KF
KH
KL
KQ
KQX
KQLZ
KQHZ
OEQ
OELZ
OEHZ
ADDRESS
(NOTE 2)
ADSC#
ADSP#
ADV#
OE#
CLK
CE#
Q
2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When
3. Timing is shown assuming that the device was not enabled before entering into this sequence. OE# does not cause Q
4. Outputs are disabled within two clock cycles after deselect.
MIN
6.0
2.3
2.3
1.5
CE# is HIGH, CE2# is HIGH and CE2 is LOW.
to be driven until after the following clock rising edge.
0
0
-6
MAX
166
3.5
3.5
3.5
3.5
t ADSS
t AS
t CES
A1
t ADSH
t AH
t CEH
t KH
(NOTE 3)
High-Z
MIN
7.5
2.5
2.5
1.5
t KC
0
0
t WS
t KL
-7.5
Single READ
t KQLZ
MAX
t WH
133
t KQ
4.0
4.2
4.2
4.2
t ADSS
A2
Q(A1)
MIN
3.0
3.0
1.5
1.0
10
t ADSH
0
t OEHZ
-10
t AAS
MAX
100
5.0
5.0
5.0
4.5
t AAH
t OELZ
t OEQ
READ TIMING
UNITS
(NOTE 1)
MHz
Q(A2)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t KQX
t KQ
20
PIPELINED, DCD SYNCBURST SRAM
Q(A2 + 1)
16Mb: 1 MEG x 18, 512K x 32/36
SYM
t
t
t
t
t
t
t
t
t
t
ADV# suspends burst.
AS
ADSS
AAS
WS
CES
AH
ADSH
AAH
WH
CEH
Micron Technology, Inc., reserves the right to change products or specifications without notice.
3
Q(A2 + 2)
MIN
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
BURST READ
-6
MAX
Q(A2 + 3)
MIN
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
-7.5
MAX
A3
Q(A2)
Burst continued with
new base address.
Burst wraps around
to its initial state.
DON’T CARE
MIN
2.0
2.0
2.0
2.0
2.0
0.5
0.5
0.5
0.5
0.5
Q(A2 + 1)
©2000, Micron Technology, Inc.
-10
Deselect
cycle.
ADVANCE
MAX
UNDEFINED
(NOTE 4)
Q(A3)
t KQHZ
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns