MT58V512V36D Micron Technology, MT58V512V36D Datasheet - Page 5

• Manufacturer Part Number: MT58V512V36D
• Description: (MT58xxxx) 16Mb SYNCBURST SRAM
• Manufacturer: Micron Technology

TQFP PIN DESCRIPTIONS
16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM
MT58L1MY18D_2.p65 – Rev 7/00
32-35, 42-50, 32-35, 42-50,
80-82, 99,
x18
100
37
36
93
94
87
88
89
98
92
64
97
86
83
–
–
81, 82, 99,
x32/x36
100
37
36
93
94
95
96
87
88
89
98
92
64
97
86
83
SYMBOL
BWa#
BWb#
BWd#
BWE#
ADV#
BWc#
GW#
CE2#
(G#)
OE#
SA0
SA1
CLK
CE#
CE2
SA
ZZ
Input Synchronous Address Inputs: These inputs are registered and must
Input Synchronous Byte Write Enables: These active LOW inputs allow
Input Byte Write Enable: This active LOW input permits BYTE WRITE
Input Global Write: This active LOW input allows a full 18-, 32-, or 36-bit
Input Clock: This signal registers the address, data, chip enable, byte
Input Synchronous Chip Enable: This active LOW input is used to enable
Input Synchronous Chip Enable: This active LOW input is used to enable
Input Snooze Enable: This active HIGH, asynchronous input causes the
Input Synchronous Chip Enable: This active HIGH input is used to enable
Input Output Enable: This active LOW, asynchronous input enables the
TYPE
Input Synchronous Address Advance: This active LOW input is used to
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meet the setup and hold times around the rising edge of CLK.
individual bytes to be written and must meet the setup and hold
times around the rising edge of CLK. A byte write enable is LOW
for a WRITE cycle and HIGH for a READ cycle. For the x18 version,
BWa# controls DQa pins and DQPa; BWb# controls DQb pins and
DQPb. For the x32 and x36 versions, BWa# controls DQa pins and
DQPa; BWb# controls DQb pins and DQPb; BWc# controls DQc pins
and DQPc; BWd# controls DQd pins and DQPd. Parity is only
available on the x18 and x36 versions.
operations and must meet the setup and hold times around the
rising edge of CLK.
WRITE to occur independent of the BWE# and BWx# lines and
must meet the setup and hold times around the rising edge of
CLK.
write enables and burst control inputs on its rising edge. All
synchronous inputs must meet setup and hold times around the
clock’s rising edge.
the device and conditions the internal use of ADSP#. CE# is
sampled only when a new external address is loaded.
the device and is sampled only when a new external address is
loaded.
device to enter a low-power standby mode in which all data in the
memory array is retained. When ZZ is active, all other inputs are
ignored. This pin has an internal pull-down and can be floating.
the device and is sampled only when a new external address is
loaded.
data I/O output drivers. G# is the JEDEC-standard term for OE#.
advance the internal burst counter, controlling burst access after
the external address is loaded. A HIGH on this pin effectively
causes wait states to be generated (no address advance). To ensure
use of correct address during a WRITE cycle, ADV# must be HIGH at
the rising edge of the first clock after an ADSP# cycle is initiated.
PIPELINED, DCD SYNCBURST SRAM
5
16Mb: 1 MEG x 18, 512K x 32/36
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DESCRIPTION
©2000, Micron Technology, Inc.
ADVANCE