MT90812 Mitel Networks Corporation, MT90812 Datasheet - Page 30

• Manufacturer Part Number: MT90812
• Description: Integrated Digital Switch (IDX)
• Manufacturer: Mitel Networks Corporation

MT90812
The MT90812 defaults to C8P input clock reference when reset. When C8P is selected as the input clock
reference the clock oscillator pins C8P_C16 and OSC can be used with an external 8.192 MHz crystal or pin
C8P_C16 can be used directly as a clock input with OSC left unconnected. Refer to Section 9.5, “C8P Pin
Timing Source”. When C8P is selected, no frame pulse is used and the MT90812 generates F4o and F8o. F4o
and F8o can be disabled by setting F4E and F8E bits low in the Output Clocking Control Register (OCC).
With C16 as the clock reference the HMVIP Frame Alignment Interface can be selected with the HMVIP bit in
the Timing Control Register (TC).
9.2
ST-Bus, GCI or HMVIP Serial Data Interface timing modes are supported on the serial streams of the
MT90812. The two local streams, STi/o0, STi/o1 operate at 2.048 Mb/s. The Expansion Bus can operate in two
modes, TDM Link and IDX Link, as described in Section 3.0. In TDM Link, EST0/1 can operate at 2, 4 or
8 Mb/s. In IDX Link, EST0/1 operates at 8 Mb/s. The incoming 8kHz frame pulse used for frame
synchronization for both local and expansion bus streams can be either ST-Bus, GCI or HMVIP format. In all
timing modes except C16-HMVIP mode, the MT90812 automatically detects the presence of an input frame
pulse on F8 or FPi pins and identifies it as either ST-Bus or GCI. For C16-HMVIP mode, the frame pulse must
be in ST-Bus format.
9.2.1
For STi/o0, STi/o1 2.048 Mb/s streams a 4.096 MHz clock is used for the serial interface timing and is
generated in the Clock Control block. The PCS bit in the TC register selects the source of this clock as either
derived from the input clock or from the PLL and is described below. In ST-Bus format, every second edge of
the 4.096 MHz clock marks the bit boundary and the data is clocked in on the rising edge the 4.096 MHz clock,
three quarters of the way into the bit cell, see Figure 40 on page 86. In GCI format, every second rising edge of
the 4.096 MHz clock marks the bit boundary and data is clocked in on the falling edge of the 4.096 MHz clock
at three quarters of the way into the bit cell, see Figure 41 on page 87.
9.2.2
The Expansion Bus can run at 2, 4 or 8Mb/s. In TDMLink, bits EP0 and EP1 of the TC register define the data
rate. In IDX Link the date rate is always 8Mb/s. In both modes the timing is similar to that used for ST0/1
streams when double rate clock is used. For example at 2, 4 and 8 MB/s rates, CLK is 4.096, 8.192 or 16.384
MHz, respectively. Refer to Figure 40 on page 86 for ST-Bus timing and Figure 41 on page 87 for GCI.
When C8 timing mode is selected, the incoming data, on the Expansion bus running at 8Mb/s, is clocked at
either the 1/2 bit time or 3/4 bit time. Fig. 42 and Fig. 43 shows the expansion bus timing with the data clocked
at the 1/2 bit time for ST-Bus and GCI, respectively. Without the presence of a 16.384 MHz input clock
reference, the PLL must be used to clock data at the 3/4 bit time. The PLL must be enabled and the PCS bit set
to 1. For further description see Section 9.2.5.
9.2.3
When C16 timing mode is selected, the HMVIP bit in the Timing Control Register (TC) enables the HMVIP
Frame Alignment Interface. The C8P_C16i input must be at 16.384 MHz, C4i must be 4.096MHz. C4i is used to
sample the 8kHz ST-Bus frame pulse. The timing relationship between the two clocks and the frame pulse is
defined in Figure 44 on page 88. In C16 Non-HMVIP mode frame synchronization is made using F8. C16/F8
timing is shown in Figure 37 on page 84 for ST-Bus and Figure 38 on page 84 for GCI.
9.2.4
The MT90812 generates C2o, F4o, C4o, F8, C8, and C10o signals. These outputs are enabled by setting the
corresponding bits in the Output Clocking Control Register (OCC) described on page 56. F8 and C8 signals
are bi-directional pins. When the C8/F8 input clock reference mode is selected they are used as inputs and the
C8E and F8E output enables of the OCC register are ignored.
26
Serial Data Interface Timing
Local Streams, STi/o0 and STi/o1
Expansion Bus, EST0/1
HMVIP Frame Alignment
Output Clock and Frame Pulse Signals
Advance Information