MT90812 Mitel Networks Corporation, MT90812 Datasheet - Page 59

• Manufacturer Part Number: MT90812
• Description: Integrated Digital Switch (IDX)
• Manufacturer: Mitel Networks Corporation

Advance Information
22.3
The timing control register is configured as follows:
Read/Write Address is: 002
Reset Value is: 20
5-4
Bit
7
6
3
2
1
0
Timing Control Register (TC)
HMVIP
CR1-0
Name
WDE
PMS
FPO
PCS
PE
H
Watchdog Enable. When 0, disables the Clock Watchdog Circuit. When 1, the Clock
Watchdog Circuit will generate an interrupt in the event of the loss of the clock at the
C8 input. See “Watchdog Timer” on page 28.
FPO. Selects ST-Bus or GCI frame alignment and polarity for outgoing frame pulse
generation. When 0, ST-Bus Frame Pulses are generated on F8o and F4o. When 1, GCI
frame pulses are generated and the polarities of C4o and C8 are inverted. The outgoing
frame pulse mode is independent of the incoming frame pulse mode.
Input Clock Reference.
00 C4
01 C8
10 C8P (default)
11 C16
Selects one of four possible clock references, C4, C8, C8P, or C16. C4 is not valid
when the PLL is not enabled. The MT90812 requires at least an 8M clock internally.
When the C4 input clock is selected the 8.192 Mhz clock is derived from the PLL.
When C8P is selected as the input clock reference no frame pulse is used and the
MT90812 generates F4o and F8o when they are enabled. Refer to Table 9, “Clock
Modes,” on page 25.
HMVIP Select. With C16 as Input Clock Reference, when HMVIP=1, enables the HMVIP
Frame Alignment interface. Otherwise, the device operates in ST-BUS/GCI mode.
PLL Enable. When 0, disables the PLL. When 1, enables the PLL. With the PLL off, C10
is disabled and C4 as an input clock reference is not valid.
PLL Mode Select. With PE=1, when PMS = 1 the PLL operates in Master Mode.
When PMS = 0, the PLL operates in Slave mode. Default Slave Mode.
PLL Clock Select. With PE=1, when PCS = 1 selects clocks generated from the PLL
for use in STi/o0, STi/o1 and incoming EST0/1 TDM streams, C2o, F4o and C4o.
Otherwise the clocks are derived directly from the Input Clock Reference. With C4 as
the input clock reference, EST0/1, 4 and 8 Mb/s timing, is generated from the PLL
independent of PCS. Refer to Table 9, “Clock Modes,” on page 25 and Section 9.2.5.
H
Description
MT90812
55