MT90812 Mitel Networks Corporation, MT90812 Datasheet - Page 53

• Manufacturer Part Number: MT90812
• Description: Integrated Digital Switch (IDX)
• Manufacturer: Mitel Networks Corporation

MT90812
Advance Information
20.0 Microprocessor Port
The MT90812 provides a parallel microprocessor interface for non-multiplex or multiplexed bus structures. This
interface is compatible with Motorola non-multiplexed/multiplexed and Intel/National multiplexed buses.
If the IM input pin is low or not connected, the device assumes its default mode (Motorola Non-multiplexed
bus). In non-multiplexed mode, the microprocessor port consists of an 8-bit parallel data bus (AD0-AD7), 10-bit
address lines (A0-A9) and four control lines (CS, DS, R/W and DTA). The parallel microprocessor port provides
the access to the control registers and the connection and data memories of the MT90812. Data Memory is
read only. The control register at location 61
( 3E1
in motorola non-muxed, 061
in in multiplexed
H
H
H
mode) must be initialized to 080
.
H
If the IM pin is high, the microprocessor port provides compatibility to MOTEL interface. In MOTEL interface,
Motorola, National, and Intel Multiplexed Bus CPU can be connected to the device. In this mode, the interface
pins are: AD<7:0> (data and address), AS/ALE (Address Latch Enable/ Address Strobe), DS/RD (Data Strobe/
Read), R/W \ WR (Read/Write\Write), CS (Chip Select) and DTA (Data Acknowledgment). The MOTEL circuit
automatically identifies the type of CPU Bus connected to the MT90812. This circuit uses the level of the DS/
RD input pin at the rising edge of the AS/ALE to identify the appropriate bus timing connected to the MT90812.
If DS/RD is low at the rising edge of AS/ALE then Motorola bus timing is selected. If DS/RD is high at the rising
edge of AS/ALE, then Intel bus timing is selected. See Figures 48 to 50 for each CPU interface timing.
A MT90812 memory address, in multiplexed microport mode, consists of two portions. The higher order bits(3)
originate from the Control Register. The lower order bits(8) originate from the address lines directly. The
address lines A6-A0, on the Control Interface, give access to the Control Registers directly if A7 is zero, or
depending on the contents of Control Register, to the High or Low sections of the Connection Memory, or to the
Data Memory. Refer to “Address Memory Map” on page 12.
Interrupts can occur from D-channel Basic Receive Transmit (DBRT), FSK, Energy Detect, Conference, or
Timing blocks. Two registers are provided to help the microprocessor deal with interrupts. The Interrupt Enable
register (INTE), allows interrupts from each source to be enabled or disabled. The Interrupt Status register
(INTS), indicates which interrupt source has generated an interrupt. For further description on the INTS and
INTE registers, refer to “Interrupt Status Register (INTS)” on page 56 and “Interrupt Enable Register (INTE)” on
page 57, respectively.
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